Abstract: The invention relates to a method of testing an integrated circuit comprising memory cells arranged around a core whose clock input is subjected to a conditional inhibition in the test mode. The method in accordance with the invention includes the following steps: configuration of the circuit in the test mode (T/R=1, TM, En=0), selection of a virtual address (Sel(DV)), canceling the inhibition (En=1) of the clock input of the core following said selection. The invention enables to transfer to the core enough clock pulses to allow the core to properly achieve the operating sequence that it should emulate, without resorting to prior storage of the number of pulses necessary for this operating sequence. The inhibition of the clock input of the core can be controlled by means of JTAG-compliant series of instructions. Application: Validation of the functioning of integrated circuits.

Abstract: The present invention relates to a method for optimization of temporal performances of a network of electronic cells, comprising a plurality of cells which are taken from a library (LIB), comprising several categories of cells, the cells of a same category all having the same functionality, and being arranged in increasing order of power.

Abstract: The invention relates to a method of testing an integrated circuit comprising memory cells arranged around a core whose clock input is subjected to a conditional inhibition in the test mode.