Patents by Inventor Philippe Bove

Philippe Bove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8519443
    Abstract: The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: August 27, 2013
    Assignees: Centre National de la Recherche Scientifique-CNRS, S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Jean-Luc Pelouard, Melania Lijadi, Christophe Dupuis, Fabrice Pardo, Philippe Bove
  • Publication number: 20100001319
    Abstract: The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 7, 2010
    Inventors: Jean-Luc Pélouard, Melania Lijadi, Christophe Dupuis, Fabrice Pardo, Philippe Bove
  • Publication number: 20070164299
    Abstract: Electronic circuits dedicated to high frequency and high power applications based on gallium nitride (GaN) suffer from reliability problems. The main reason is a non-homogenous distribution of the electronic density in these structures that originates from alloy disorders at the atomic and micrometric scale. This invention provides processes for manufacturing semiconducting structures based on nitrides of Group III elements (Bal, Ga, In)/N which are perfectly ordered along a preferred crystalline axis. To obtain this arrangement, the ternary alloy barrier layer is replaced by a barrier layer composed of alternations of binary alloy barrier layers. The lack of fluctuation in the composition of these structures improves electron transport properties and makes the distribution more uniform.
    Type: Application
    Filed: March 12, 2007
    Publication date: July 19, 2007
    Inventors: Hacene Lahreche, Philippe Bove