Abstract: A method for interconnecting a multilayer metal network of an electronic circuit board is provided. In the method, the electronic circuit board is made up of a plurality of superimposed metal layers having an insulating layer disposed therebetween, wherein the material of the insulating layer is substantially inert to a catalytic activation bath and to chemical deposition of metal. A via hole is formed in the board having a first metal layer thereof as its bottom and traversing a second metal layer and using electroless deposition, metal is deposited in the via by growing the metal from the metal layers only.

Abstract: Via studs (23) of the multi-layer structure (12) are formed on a uniform metal layer that is subsequently etched to form the conductors (17) of a conductive layer of the multi-layer structure.

Abstract: A method for deposition of an insulating layer on a conductive layer of the multi layer structure of a connection board of a VLSI circuit and a connection board formed by the method. The formation of an insulating layer coplanar with the upper surface of the vias (21) of the conductive layer (16a, 16b) is done by etching of an insulating layer (26) formed of a plurality of successive strata (22, 23, 24, 25) until a surface is obtained that has steps of a maximum height (S4) substantially equal to or less than a desired valve (V) corresponding to the desired degree of planarity of the final insulating layer.

Abstract: In a high-density integrated circuit having a multilayered metal interconnection network, a planarization layer is formed over a lower metal layer which includes conductors having steep edges by chemically depositing a dielectric layer in the vapor phase over the lower metal layer so as to fill up hollows formed in the dielectric layer in intervals between the conductors, spreading a viscous layer of spin-on-glass over the dielectric layer, annealing the spin-on-glass layer to form a compact mass, forming vias through the spin-on-glass and dielectric layers to the conductors, and applying an upper metal layer over the spin-on-glass layer so as to fill the vias and provide electrical contacts to the conductors of the lower metal layer.

Abstract: A method of forming a planarization layer over a multilayered metal network which interconnects the components of a high-density integrated circuit and which includes conductors having steep edges disposed over a substrate. A layer of spin-on-glass is applied over the lower metal layer so as to have a thickness substantially equal to that of the lower metal layer and to form a thin film over the conductors. The spin-on-glass layer is uniformly etched to expose the upper surfaces of the conductors, and a dielectric layer is applied onto the etched spin-on-glass layer and upper surfaces of the conductors.