Patents by Inventor Philippe CONTI

Philippe CONTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS, APPARATUS, AND SYSTEMS FOR SECURE DEMAND PAGING AND OTHER PAGING OPERATIONS FOR PROCESSOR DEVICES
    Publication number: 20150032951
    Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).
    Type: Application
    Filed: August 13, 2014
    Publication date: January 29, 2015
    Inventors: Steven Goss, Gregory Remy Philippe Conti, Narendar M. Shankar, Mehdi-Laurent Akkar, Aymeric Vial
  • System and method of identifying and preventing security violations within a computing system
    Patent number: 8220045
    Abstract: A system and method of identifying and preventing security violations within a computing system. Some exemplary embodiments may be a method comprising monitoring activity on a core bus coupled to a processor core (the processor core operating in a computing system), identifying activity on the core bus as a security violation, and preventing execution of an instruction within the processor core in response to the security violation.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: July 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema
  • Method and system for detecting a security violation using an error correction code
    Patent number: 7263617
    Abstract: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword, determining a total number of codeword errors from the ELP, and preventing access to the data within the codeword if the total number of codeword errors exceeds a maximum number of correctable errors.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema Le Cellini
  • Method and system of verifying proper execution of a secure mode entry sequence
    Publication number: 20060005072
    Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
    Type: Application
    Filed: October 8, 2004
    Publication date: January 5, 2006
    Inventors: Gregory Philippe Conti, Jerome Azema