Abstract: The invention relates to a locating device for locating a computer cabinet from among a plurality of computer closets, the computer cabinet including a display unit which displays a status of the cabinet in accordance with the statuses of the devices in the cabinet.

Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: The subject of the invention is in particular the direct transfer of data between first and second peripherals connected via a communication bus. For this purpose, the first peripheral comprises a controller for direct access to a memory having means (425) for initiating at least one command for direct access to a region of a memory external to said first peripheral and means (400) for receiving at least one command for direct access to a region of a memory of said first peripheral, said command being received from said at least one second peripheral, and means (415) for transmitting said at least one received direct access command to a component of said first peripheral. The controller thus allows a controller of direct access to a memory of said at least one second peripheral to carry out a direct transfer of at least one data item to or from a memory of said first peripheral from or to said second peripheral.

Abstract: The invention relates in particular to a computer system including peripheral devices (600) and at least one switch (605) connected to each device. A first device includes a means for initiating a control of direct access to memory areas, each one of which is associated with a separate element of the system. The switch includes a means for transmitting at least a portion of the control to each element. At least one element comprises a second device including a means for receiving at least one control of direct access to a memory area of said second device, said control being received from said first device via said switch, and a means for transmitting said received control to a component of said second device. Said system allows said first device to perform a direct data transfer to or from a memory of said first peripheral device from or to each element.

Abstract: A computer system for managing the execution of threads including at least one central processing unit which performs interleaved execution of a plurality of threads throughout a plurality of virtual processors from said same central processing unit, and a handler for distributing the execution of the threads throughout the virtual processors. The computer system further includes means for classifying threads to be executed according to several predetermined types, and the handler for distributing the execution of threads directs each thread to be executed to a virtual processor according to the type thereof.

Abstract: Methods and devices for characterizing the interconnection efficiency of a computer network based upon a static routing scheme are disclosed. The network comprises a plurality of items of equipment. After having determined (105) a plurality of types of links between said items of equipment, a theoretical number of routes per link and the associated number of links are determined (120, 125) for each type of at least one subset of said plurality of types of links according to the topology of said network. The determined theoretical number of routes per link and the associated number of links are then aggregated (135) to estimate at least one optimal routing point characterizing the theoretical efficiency of the network. Such optimal routing points can be compared with estimated actual routing points based upon the aggregation of actual numbers of routed per link and associated actual numbers of links to characterizes the network efficiency.

Abstract: The present invention relates to a computer device with synchronization barrier. The device comprises a memory and a processing unit, capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, said blocks being associated by groups in successive work steps, The device further comprises a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Abstract: A network recognition system for identifying a storage unit of a plurality of network storage subsystems of a machine (1) including at least one local coupler (11) for exchanging data with the storage subsystems (5, 6, 7) of the network recognition system, each storage subsystem (5, 6, 7) having at least one storage unit identifiable by means of a logical unit number (LUN). An object (100) corresponding to the machine (1) has an object (101) corresponding to the local coupler (11) of the machine (1). Object (101) includes an object (111) corresponding to a remote coupler (51, 52) of one of the storage subsystems (5). Object (101) includes a method (116) for obtaining the object (111) and a list of objects (118, 119) each corresponding to a logical unit number (LUN) identifying a storage unit of the subsystem (5) accessible through the local coupler (11).