Patents by Inventor Philippe Damon
Philippe Damon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10084893Abstract: Embodied is a host network controller for a network processor. The host network controller is adapted to implement a finite state machine for an operation adhering to a standardized communication protocol, wherein the finite state machine has fewer possible states than those defined for the operation in accordance with the standardized communication protocol.Type: GrantFiled: September 17, 2015Date of Patent: September 25, 2018Assignee: International Business Machines CorporationInventors: Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Patent number: 10033633Abstract: A network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyzes a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.Type: GrantFiled: November 2, 2015Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Patent number: 10015291Abstract: Provided is a method for operating a host network controller for a network processor where the host network controller has at least one register. A restricted set of state data may be stored in at least one register. The restricted set of state data may be indicative of fewer possible states than those defined in accordance with a standardized communication protocol. The host network controller may implement a finite state machine based on the restricted set of state data stored in the at least one register such that the finite state machine may have fewer possible states than those defined in accordance with the standardized communication protocol.Type: GrantFiled: September 17, 2015Date of Patent: July 3, 2018Assignee: International Business Machines CorporationInventors: Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Patent number: 9917932Abstract: A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected.Type: GrantFiled: February 22, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Patent number: 9917929Abstract: A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected.Type: GrantFiled: November 4, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Patent number: 9893990Abstract: A network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyzes a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.Type: GrantFiled: September 18, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20160173656Abstract: A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20160134462Abstract: Provided is a method for operating a host network controller for a network processor where the host network controller has at least one register. A restricted set of state data may be stored in at least one register. The restricted set of state data may be indicative of fewer possible states than those defined in accordance with a standardized communication protocol. The host network controller may implement a finite state machine based on the restricted set of state data stored in the at least one register such that the finite state machine may have fewer possible states than those defined in accordance with the standardized communication protocol.Type: ApplicationFiled: September 17, 2015Publication date: May 12, 2016Inventors: Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20160134529Abstract: Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.Type: ApplicationFiled: November 2, 2015Publication date: May 12, 2016Inventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20160134471Abstract: Embodied is a host network controller for a network processor. The host network controller is adapted to implement a finite state machine for an operation adhering to a standardized communication protocol, wherein the finite state machine has fewer possible states than those defined for the operation in accordance with the standardized communication protocol.Type: ApplicationFiled: September 17, 2015Publication date: May 12, 2016Inventors: Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20160134549Abstract: A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected.Type: ApplicationFiled: November 4, 2015Publication date: May 12, 2016Inventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20160134559Abstract: Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.Type: ApplicationFiled: September 18, 2015Publication date: May 12, 2016Inventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
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Patent number: 9088594Abstract: A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.Type: GrantFiled: February 3, 2012Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Patent number: 8949856Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.Type: GrantFiled: May 10, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Publication number: 20140337677Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Patent number: 8867395Abstract: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.Type: GrantFiled: August 9, 2012Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Francois Abel, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Fabrice J. Verplanken
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Patent number: 8854996Abstract: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.Type: GrantFiled: July 15, 2011Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Francois Abel, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Fabrice J. Verplanken
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Patent number: 8576864Abstract: A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode.Type: GrantFiled: January 21, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Patent number: 8468546Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.Type: GrantFiled: February 3, 2012Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Publication number: 20120300642Abstract: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicant: International Business Machines CorporationInventors: Francois Abel, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Fabrice J. Verplanken