Patents by Inventor Philippe Delpech
Philippe Delpech has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9003717Abstract: The invention relates to a ventilation well with hurricane-resistant function for a building comprising an inclined roof (11), intended to be adapted to said building in such a way as to extend over its entire height, communicating towards the exterior of the building at the peak of the roof, and having at least one lateral opening (3, 4) communicating with the inside volume of the building, characterized in that it further comprises a cap (5) which may be adjustable in height and/or removable at the top of the well.Type: GrantFiled: March 21, 2013Date of Patent: April 14, 2015Assignee: Centre Scientifique et Technique du BatimentInventors: Christian Barre, Jean-Paul Bouchet, Philippe Delpech, Marc Dufresne de Virel, Gerard Grillaud, Olivier Flamand
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Patent number: 8981551Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.Type: GrantFiled: September 20, 2013Date of Patent: March 17, 2015Assignee: STMicroelectronics (Crolles 2) SASInventors: Philippe Delpech, Eric Sabouret, Sebastien Gallois-Garreignot
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Publication number: 20140091451Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.Type: ApplicationFiled: September 20, 2013Publication date: April 3, 2014Applicant: STMicroelectronics (Crolles 2) SASInventors: Philippe Delpech, Eric Sabouret, Sebastien Gallois-Garreignot
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Publication number: 20130283708Abstract: The invention relates to a ventilation well with hurricane-resistant function for a building comprising an inclined roof (11), intended to be adapted to said building in such a way as to extend over its entire height, communicating towards the exterior of the building at the peak of the roof, and having at least one lateral opening (3, 4) communicating with the inside volume of the building, characterised in that it further comprises a cap (5) which may be adjustable in height and/or removable at the top of the well.Type: ApplicationFiled: March 21, 2013Publication date: October 31, 2013Applicant: CENTRE SCIENTIFIQUE ET TECHNIQUE DU BATIMENTInventors: Christian BARRE, Jean-Paul BOUCHET, Philippe DELPECH, Marc DUFRESNE DE VIREL, Gerard GRILLAUD, Olivier FLAMAND
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Publication number: 20110272801Abstract: A semiconductor device includes an integrated circuit and external electrical connection pads. Each pad includes cavities that are at least partially filled with a material different from the material forming the pads, so as to form inserts.Type: ApplicationFiled: May 4, 2011Publication date: November 10, 2011Applicants: STMICROELECTRONICS S.A., STMICROELECTRONICS (CROLLES 2) SASInventors: Vincent Fiori, Philippe Delpech, Eric Sabouret
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Patent number: 7916449Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.Type: GrantFiled: June 6, 2008Date of Patent: March 29, 2011Assignee: STMicroelectronics SAInventors: Sébastien Cremer, Philippe Delpech, Sylvie Bruyere
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Patent number: 7667292Abstract: An integrated circuit includes at least one capacitor that is formed on a layer provided with at least one first trench. The capacitor, which is provided with a dielectric layer that separates two electrodes, conforms to the shape of the first trench, but leaves a part of the first trench unfilled. A material capable of absorbing stresses associated with the displacements of the walls of the trench is placed in the trench to fill the part of the first trench. A second trench is formed at least partly surrounding the first trench. This second trench is also at least partly filled with a material capable of absorbing stresses associated with the displacements of the walls of the second trench. A void may be included in the stress absorbing material which fills either of the first or second trenches.Type: GrantFiled: May 1, 2006Date of Patent: February 23, 2010Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Jean-Christophe Giraudin, Vincent Fiori, Philippe Delpech
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Patent number: 7563687Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.Type: GrantFiled: December 14, 2005Date of Patent: July 21, 2009Assignee: STMicroelectronics S.A.Inventors: Jean-Christophe Giraudin, Sébastien Cremer, Philippe Delpech
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Publication number: 20090040684Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.Type: ApplicationFiled: June 6, 2008Publication date: February 12, 2009Applicant: STMicroelectronics SAInventors: Sebastien Cremer, Philippe Delpech, Sylvie Bruyere
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Patent number: 7479424Abstract: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.Type: GrantFiled: April 17, 2006Date of Patent: January 20, 2009Assignee: STMicroelectronics S.A.Inventors: Jean-Christophe Giraudin, Sébastien Cremer, Philippe Delpech
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Publication number: 20080157273Abstract: An integrated electronic circuit chip having an inductor placed above a protective layer for the metallization levels of the chip, the inductor having a thickness in a direction perpendicular to a surface of a substrate of the chip. The inductor has a reduced electrical resistance and a high quality factor. In addition, an inductor is realized at the same time as the pads for connecting the chip to a supporting board using flip-chip technology.Type: ApplicationFiled: December 27, 2007Publication date: July 3, 2008Applicant: STMICROELECTRONICS SAInventors: Jean-Christophe Giraudin, Philippe Delpech, Jacky Seiller
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Patent number: 7378692Abstract: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.Type: GrantFiled: April 27, 2006Date of Patent: May 27, 2008Assignee: STMicroelectronics SAInventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
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Patent number: 7282803Abstract: An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed between the capacitor and the semiconductor component. Preferably, the semiconductor component is placed in proximity to the surface of the substrate and several superposed layers of insulating material cover the surface of the substrate and the semiconductor component. The capacitor is then placed within at least one layer of insulating material above the semiconductor component, and the screen is placed within an intermediate layer of insulating material between the layer incorporating the capacitor and the surface of the substrate.Type: GrantFiled: May 2, 2003Date of Patent: October 16, 2007Assignee: STMicroelectronics S. A.Inventors: Andréa Cathelin, Christophe Bernard, Philippe Delpech, Pierre Troadec, Laurent Salager, Christophe Garnier
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Patent number: 7202137Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.Type: GrantFiled: May 20, 2004Date of Patent: April 10, 2007Assignee: STMicroelectronics SAInventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
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Publication number: 20060255427Abstract: An integrated circuit includes at least one capacitor that is formed on a layer provided with at least one first trench. The capacitor, which is provided with a dielectric layer that separates two electrodes, conforms to the shape of the first trench, but leaves a part of the first trench unfilled. A material capable of absorbing stresses associated with the displacements of the walls of the trench is placed in the trench to fill the part of the first trench. A second trench is formed at least partly surrounding the first trench. This second trench is also at least partly filled with a material capable of absorbing stresses associated with the displacements of the walls of the second trench. A void may be included in the stress absorbing material which fills either of the first or second trenches.Type: ApplicationFiled: May 1, 2006Publication date: November 16, 2006Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Jean-Christophe Giraudin, Vincent Fiori, Philippe Delpech
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Publication number: 20060234464Abstract: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.Type: ApplicationFiled: April 17, 2006Publication date: October 19, 2006Applicant: STMicroelectronics S.A.Inventors: Jean-Christophe Giraudin, Sebastien Cremer, Philippe Delpech
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Publication number: 20060189057Abstract: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.Type: ApplicationFiled: April 27, 2006Publication date: August 24, 2006Applicant: STMicroelectronics SAInventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
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Publication number: 20060160319Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.Type: ApplicationFiled: December 14, 2005Publication date: July 20, 2006Applicant: STMicroelectronics S.A.Inventors: Jean-Christophe Giraudin, Sebastien Cremer, Philippe Delpech
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Patent number: 7033887Abstract: A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.Type: GrantFiled: May 20, 2004Date of Patent: April 25, 2006Assignee: STMicroelectronics SAInventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer
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Patent number: 6972451Abstract: A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.Type: GrantFiled: May 14, 2003Date of Patent: December 6, 2005Assignee: STMicroelectronics S.A.Inventors: Philippe Delpech, Sébastien Cremer, Michel Marty