Abstract: A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M?N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.

Abstract: A high voltage switching regulator has significantly reduced current sensing delay between measurement of input current and generation of sensed current values, while maintaining good accuracy of the current through a power transistor using current replication and a current conveyor. High sensing accuracy of the input current ensures good load regulation, and low sensing delay ensures fixed duty cycle over a wide range of output currents and high input to output voltage ratios. A current conveyor is used to transfer high side current values to low side control circuits, e.g., pulse width modulation (PWM) control. The current conveyor is always on, e.g., some current flow is always present, thus minimizing any current measurement delay. This is accomplished by dynamically biasing the current conveyor by draining to ground a current equal to the sensed current. Wherein balancing of the current conveyor is ensured and offset at the input of the current conveyor is minimized.

Abstract: A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M-N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M?N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log 2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract: A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.

Abstract: A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.

Abstract: A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M?N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract: An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.

Abstract: A differential input operational amplifier has a voltage clamp differential transistor pair coupled to an input differential transistor pair of the operational amplifier. The voltage clamp differential transistor pair limits the output voltage of the operational amplifier by taking over control of the operational amplifier circuits from the input differential transistor pair as the output voltage approaches a clamp voltage value. A reference voltage may be used to set the output voltage at which the input differential transistor pair will be clamped by the voltage clamp differential transistor pair. Below the clamp voltage, operation of the input differential transistor pair will not be affected. At the clamp voltage the input differential transistor pair will no longer control the output of the differential amplifier, rather the voltage clamp differential transistor pair will control the maximum voltage output of the differential amplifier.

Abstract: An electrostatic discharge (ESD) structure having increased voltage withstand at an output terminal of an integrated circuit device has a thin gate oxide layer metal oxide semiconductor (MOS) device coupled in series with a thicker gate oxide layer MOS device. The thin gate oxide layer MOS device may be controlled by a low voltage control circuit of the integrated circuit. The thicker gate oxide layer MOS device may be coupled to an output of the integrated circuit device or a bipolar transistor may be coupled between the output of the integrated circuit device and the thicker gate oxide layer MOS device. The thin gate oxide layer and thicker gate oxide layer MOS devices may be coupled in series.

Abstract: A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*VREF, C*VREF/2, 0, ?C*VREF/2 and ?C*VREF. When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN?VREF/2 and A*VIN?VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

Abstract: An electronic amplifier circuit comprising an operational amplifier circuit, such as a two-stage operational amplifier circuit, in tandem with a operational transconductance amplifier. The electronic amplifier circuit has high open-loop gain and high gain-bandwidth while maintaining stability over a wide range of operating parameters.