Patents by Inventor Philippe Dollo

Philippe Dollo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7944945
    Abstract: Apparatus (D1) is dedicated to processing STM-n/STS-m type data frames in a communications network. It comprises at least one STM-n/STS-m interface unit (LIU1) adapted to receive STM-n/STS-m type data frames from a communications network and processor means (MTj) adapted, on receiving data from an STM-n/STS-m frame coming from said line interface unit (LIU1): i) to segment the whole of said received frame into m groups of p successive bytes; ii) then to associate with each group a control header containing data representing its position within the STM-n/STS-m frame; and iii) to encapsulate each group and the associated control header in a payload data field of an Ethernet frame.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 17, 2011
    Assignee: Alcatel
    Inventors: Philippe Dollo, Yannick Stephan
  • Patent number: 7751433
    Abstract: Apparatus is dedicated to switching data packet frames of different types coming from at least two transport networks that use different transport protocol layers.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 6, 2010
    Assignee: Alcatel Lucent
    Inventors: Philippe Dollo, Yannick Stephan
  • Patent number: 7706413
    Abstract: A synchronization system (D) for equipment of a synchronous transport network comprises, firstly, a first synchronization module (MA) comprising i) a first submodule (SM1A) delivering a first intermediate clock signal derived from a first external reference clock signal or an internal reference clock signal, ii) a second submodule (SM2A) delivering a first main reference clock signal derived from the first intermediate clock signal or a second intermediate clock signal, and iii) a third submodule (SM3A) delivering a first output reference clock signal derived from the first main reference clock signal or a second main reference clock signal, and, secondly, a second synchronization module (MB) comprising i) a first submodule (SM1B) delivering the second intermediate clock signal derived from another first external reference clock signal and another internal reference clock signal, ii) a second submodule (SM2B) delivering the second main reference clock signal derived from the first or the second intermediate c
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: April 27, 2010
    Assignee: Alcatel
    Inventors: Philippe Dollo, Yannick Stephan, Benoit Morin
  • Publication number: 20070160042
    Abstract: Apparatus (A) is dedicated to switching data packet frames of different types coming from at least two transport networks (N1, N2) that use different transport protocol layers.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 12, 2007
    Applicant: Alcatel Lucent
    Inventors: Philippe Dollo, Yannick Stephan
  • Publication number: 20070002901
    Abstract: Apparatus (D1) is dedicated to processing STM-n/STS-m type data frames in a communications network. It comprises at least one STM-n/STS-m interface unit (LIU1) adapted to receive STM-n/STS-m type data frames from a communications network and processor means (MTj) adapted, on receiving data from an STM-n/STS-m frame coming from said line interface unit (LIU1): i) to segment the whole of said received frame into m groups of p successive bytes; ii) then to associate with each group a control header containing data representing its position within the STM-n/STS-m frame; and iii) to encapsulate each group and the associated control header in a payload data field of an Ethernet frame.
    Type: Application
    Filed: June 16, 2006
    Publication date: January 4, 2007
    Inventors: Philippe Dollo, Yannick Stephan
  • Publication number: 20060182211
    Abstract: A synchronization system (D) for equipment of a synchronous transport network comprises, firstly, a first synchronization module (MA) comprising i) a first submodule (SM1A) delivering a first intermediate clock signal derived from a first external reference clock signal or an internal reference clock signal, ii) a second submodule (SM2A) delivering a first main reference clock signal derived from the first intermediate clock signal or a second intermediate clock signal, and iii) a third submodule (SM3A) delivering a first output reference clock signal derived from the first main reference clock signal or a second main reference clock signal, and, secondly, a second synchronization module (MB) comprising i) a first submodule (SM1B) delivering the second intermediate clock signal derived from another first external reference clock signal and another internal reference clock signal, ii) a second submodule (SM2B) delivering the second main reference clock signal derived from the first or the second intermediate c
    Type: Application
    Filed: March 28, 2005
    Publication date: August 17, 2006
    Inventors: Philippe Dollo, Yannick Stephan, Benoit Morin