Patents by Inventor Philippe Dreux

Philippe Dreux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock signal synchronization and disturbance detector
    Patent number: 9251379
    Abstract: An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 2, 2016
    Assignee: STMicroelectronics Rousset SAS
    Inventor: Philippe Dreux
  • Programmable address generator
    Patent number: 6985402
    Abstract: A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising: at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count; at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed; and an adder of the first address with the counter results, said adder providing said second address.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 10, 2006
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Dreux
  • Programmable address generator
    Publication number: 20040174766
    Abstract: A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising: at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count; at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed; and an adder of the first address with the counter results, said adder providing said second address.
    Type: Application
    Filed: December 17, 2003
    Publication date: September 9, 2004
    Applicant: STMicroelectronics S.A.
    Inventor: Philippe Dreux