Abstract: A line amplifier for static RAM memory in CMOS technology comprises first and second branches formed by a first plurality of transistors (TP.sub.1, TN.sub.1, TN.sub.2) and a second plurality of transistors (TP.sub.2, TN.sub.3, TN.sub.2), respectively. The branches are connected in series between the power supply (Vdd) and reference voltage (Vss). A positive feedback is produced by direct connection through internal nodes, and an evaluation switching transistor makes it possible to equalize the values of the voltages on the internal nodes at equilibrium. Under read control (CL), the transistor (TN.sub.2) makes it possible to amplify the preliminary difference between voltage levels due to a transition of the bit signal (D) and complemented bit signal (D) applied to the internal nodes. A precharge transistor (TN.sub.4) is common to the first and second branches and thus allows an increase in switching speed.