Abstract: A device for collecting a fraction of the perspiration excreted by a subject, the device being of the type including a multi-layer patch including: —a first layer including at least one perspiration-collecting aperture and a transfer opening; —a hydrophilic absorbent layer, positioned above the first layer and communicating with the external environment, and communicating with the first layer via the transfer opening; —a film, possibly transparent, that constitutes a barrier against water and against vapour, and that covers at least the upper face of the absorbent layer; the device notably including means for regulating the rate at which perspiration in the liquid and/or vapour state penetrates into the absorbent layer.

Abstract: A method for geolocating a terminal of a wireless communication system. The terminal receiving a message transmitted by a transmitting device of interest. An ambiguous item of identification information is obtained from the transmitting device of interest. The terminal transmitting to the access network a message including the ambiguous item of identification information from the transmitting device of interest. The access network estimating an approximate geographical position of the terminal. The transmitting device of interest is identified in a table storing a list of transmitting device identifiers and the respective geographical positions of the transmitting devices. The precise geographical position of the terminal is estimated according to the geographical position of said transmitting device of interest.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: Methods and reagents for the formation of disulfide bonds, particularly in proteins, peptides and amino acids. The methods and reagents are particularly useful for the controlled glycosylation of proteins, peptides and amino acids. The methods utilize thiosulfonate or selenenylsulfide compounds as reagents or intermediates. Some proteins and peptides comprising selenenyl-sulfide groups also form part of the invention.

Abstract: A method of processing a semiconductor substrate (3) comprises spinning the semiconductor substrate (3) while dispensing a reactive etching agent (7) onto a first surface of the spinning substrate (3) to etch a first region (8) of the surface (3). Simultaneously, a neutralising agent (9) is dispensed onto the first surface to neutralise etching agent (9) that has flowed away from the first region (8) of the surface (3), thereby substantially preventing processing of another region (10) of the first surface located nearer an edge of the substrate (3) than is the first region (8). The processing may be etching.

Abstract: Methods and reagents for the formation of disulfide bonds, particularly in proteins, peptides and amino acids. The methods and reagents are particularly useful for the controlled glycosylation of proteins, peptides and amino acids. The methods utilise thiosulfonate or selenenylsulfide compounds as reagents or intermediates. Some proteins and peptides comprising selenenyl-sulfide groups also form part of the invention.