Patents by Inventor Philippe Garrault

Philippe Garrault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Generation of input/output models
    Patent number: 8196075
    Abstract: A process is provided for creating an input/output (I/O) model. A set of logical I/O pins of an unplaced and unrouted circuit design is determined. Pin placement is determined for one or more of the logical I/O pins on device pins of a target device. An I/O pin profile for each of the logical I/O pins is determined. A plurality of I/O pin models available on the target device are input and an I/O pin model is selected from the plurality of I/O pin models for each of the logical I/O pins according to the respective I/O pin profiles. An I/O model is generated including each selected I/O pin model within the I/O model. The generated I/O model is stored in a processor readable storage medium.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: June 5, 2012
    Assignee: Xilinx, Inc.
    Inventors: Philippe Garrault, Jennifer D. Baldwin, Richard J. LeBlanc, Premduth Vidyanandan, Kenneth J. Stickney, Jr., Carrie L. Kisiday
  • Generating a design-specific input/output model document
    Patent number: 7882484
    Abstract: A method of creating a design-specific I/O model document can include reading a plurality of I/O pin models corresponding to available I/O pin profiles on a target device (355) and identifying I/O pins of the target device that are used by a circuit design (325). An I/O pin profile for each I/O pin of the target device that is used by the circuit design can be determined (345). An I/O pin model can be selected from the plurality of I/O pin models for each I/O pin of the target device that is used by the circuit design according to the I/O pin profiles (355). The design-specific I/O model document for the circuit design can be generated by including each selected I/O pin model within the design-specific I/O model document (365). The design-specific I/O model document can be output (380).
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: February 1, 2011
    Assignee: Xilinx, Inc.
    Inventors: Jennifer D. Baldwin, Paul Cheng, Philippe Garrault, Hari Devanath