Abstract: The invention relates to the field of imaging, diagnostic, internal vectorized radiotherapy and nuclear medicine. Inventors herein describe new products for use for labelling, detecting and/or imaging angiogenesis, vasculogenesis or a tissue or organ expressing the APJ receptor; for use for detecting, measuring, diagnosing, staging and/or monitoring angiogenesis, vasculogenesis, an angiogenesis- and/or vasculogenesis-related disease or disorder, and/or a disease or disorder inducing or modulating the expression of a APJ receptor in a tissue or organ; for use for preventing or treating angiogenesis, vasculogenesis, an angiogenesis- and/or vasculogenesis-related disease or disorder, and/or a disease or disorder inducing or modulating the expression of a APJ receptor in a tissue or organ; or for use for evaluating or monitoring the therapeutic effect of an angiogenic or antiangiogenic treatment or of an APJ receptor-targeted treatment.

Abstract: The invention relates to a process for assignment, by an addressing server for a network, of a network address to a terminal network-element connected to one of the connection ports of one of the interconnection network-elements of said network, comprising: transmission of a network address request by said terminal network-element to said interconnection network-element, the determination by said interconnection network-element of a location of said terminal network-element where said location combines a topological identifier for said interconnection network-element with at least one identifier for said connection port, the transmission by said interconnection network-element to said addressing server of said request with said location, assignment by said addressing server to said terminal network-element of said network address based on said location.

Abstract: A method designed to configure an IT system having at least one computing core for executing instruction threads, in which each computing core is capable of executing at least two instruction threads at a time in an interlaced manner, and an operating system, being executed on the IT system, capable of providing instruction threads to each computing core. The method includes a step of configuring the operating system being executed in a mode in which it provides each computing core with a maximum of one instruction thread at a time.

Abstract: A method designed to configure an IT system having at least one computing core for executing instruction threads, in which each computing core is capable of executing at least two instruction threads at a time in an interlaced manner, and an operating system, being executed on the IT system, capable of providing instruction threads to each computing core. The method includes a step of configuring the operating system being executed in a mode in which it provides each computing core with a maximum of one instruction thread at a time.

Abstract: The invention relates to a process for assignment, by an addressing server for a network, of a network address to a terminal network-element connected to one of the connection ports of one of the interconnection network-elements of said network, comprising: transmission of a network address request by said terminal network-element to said interconnection network-element, the determination by said interconnection network-element of a location of said terminal network-element where said location combines a topological identifier for said interconnection network-element with at least one identifier for said connection port, the transmission by said interconnection network-element to said addressing server of said request with said location, assignment by said addressing server to said terminal network-element of said network address based on said location.

Abstract: The invention relates in particular to the optimization of the execution of a software application in a system having multiprocessor architecture including a plurality of input/output controllers and secondary processing units. After determining (300) the system topology, a call to a function to be executed by a secondary processing unit is intercepted (305). The main processor that generated said call is identified (310). A secondary processing unit is then identified (315) according to the main processor identified and according to the topology of said system. Advantageously, the secondary processing unit thus identified is the secondary processing unit that is the closest to the identified main processor. The call is then modified (320) in order to force the execution of at least one part of the function called in the identified secondary processing unit.

Abstract: A method designed to configure an IT system having at least one computing core for executing instruction threads, in which each computing core is capable of executing at least two instruction threads at a time in an interlaced manner, and an operating system, being executed on the IT system, capable of providing instruction threads to each computing core. The method includes a step of configuring the operating system being executed in a mode in which it provides each computing core with a maximum of one instruction thread at a time.

Abstract: The invention relates in particular to the optimisation of the execution of a software application in a system having multiprocessor architecture including a plurality of input/output controllers and secondary processing units. After determining (300) the system topology, a call to a function to be executed by a secondary processing unit is intercepted (305). The main processor that generated said call is identified (310). A secondary processing unit is then identified (315) according to the main processor identified and according to the topology of said system. Advantageously, the secondary processing unit thus identified is the secondary processing unit that is the closest to the identified main processor. The call is then modified (320) in order to force the execution of at least one part of the function called in the identified secondary processing unit.

Abstract: A process, a tool and a computer for analyzing and locating hardware failures in a computing machine storing information on operational errors generated by the various sensible hardware components of the machine, characterized in that it consists of creating a man/machine interface (I) through which the components and the rules for interpreting errors are described in a structural language and used by the machine as external parameters in correlation with the error information to detect the malfunctioning component or components. The preventive process is particularly adopted for computer hardware maintenance.

Abstract: In a computer platform (PF) comprising at least one unit (M1, M2), each including at least one respective processor (PRO1-PRO2, PRO3-PRO5) and at least one respective interrupt controller (CI1, CI2), and an operating system (SE) including a basic kernel (NOY) for creating extension modules external to said basic kernel, at least one interrupt managing extension module (MEX1, MEX2) external to the basic kernel (NOY) is created in order to relieve the basic kernel of the management of interruptions.

Abstract: In a computer platform (PF) comprising at least one unit (M1, M2), each including at least one respective processor (PRO1-PRO2, PRO3-PRO5) and at least one respective interrupt controller (CI1, CI2), and an operating system (SE) including a basic kernel (NOY) for creating extension modules external to said basic kernel, at least one interrupt managing extension module (MEX1, MEX2) external to the basic kernel (NOY) is created in order to relieve the basic kernel of the management of interruptions.