Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Abstract: The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells.

Abstract: A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.

Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.

Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Abstract: A non-volatile memory device includes a memory plane formed from a matrix of memory cells, each including an access transistor and a capacitor. The matrix includes first and second groups of cells laid out in a first and second directions. Each first group includes cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together. The device includes control means capable of applying chosen voltages to the first, second, and third metallizations so as to selectively program a single one of the cells by damaging its dielectric without programming the other cells and without damaging the transistors of the cells.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: A non-volatile memory device is provided that can be irreversibly programmed electrically. The device includes a memory plane formed from a matrix of memory cells, with each of the memory cells including an access transistor and a capacitor. The memory cell matrix includes first groups of memory cells laid out in a first direction and second groups of memory cells laid out in a second direction. Each first group includes memory cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes memory cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together.