Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: The present invention refers to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: A MOSFET device arranged on a substrate 10 having first and second heavily-doped strips 11 and 14 respectively covered by first and second contacts 13 and 15, these two strips being spaced apart by a channel 18 that also appears on the substrate 10, the channel being covered by a dielectric layer 20, itself surmounted by a third contact 21. The channel 18 incorporates a thin film 19 lightly doped with dopant atoms of a same type as the channel, at the interface with the dielectric layer 20, the dopant atoms being distributed on both sides of the interface.

Abstract: The present invention refers to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water.

Abstract: The invention concerns a method for producing a field effect transistor having a trench gate comprising: —the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, —the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, —the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, —the oxidation (160) of the layer of polycrystalline silicon, and —the metallization (180) of the substrate on the front and rear faces of same in order to form active source and drain areas.

Abstract: The invention concerns a method for producing a field effect transistor having a trench gate comprising:—the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face,—the primary implantation (120) of ions having a second type of conducitivity so as to implant each trench of the substrate to form an active gate area,—the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area,—the oxidation (160) of the layer of polycrystalline silicon, and—the metallisation (180) of the substrate on the front and rear faces of same in order to form active source and drain areas.

Abstract: A system for supplying direct current and DC voltage is provided. The system comprise a first supply branch having a first DC voltage source and a power field-effect transistor of a current limiter which are connected in series, and a second supply branch having a second DC voltage source. The power transistor has a current/voltage characteristic with a first inverse polarization area without current limitation, and a second conduction area with current limitation based on a current threshold. The power field-effect transistor is connected to the first voltage source with an inverse polarization when the voltage source of the first branch is operating normally.

Abstract: A system for supplying direct current and DC voltage is provided. The system comprise a first supply branch having a first DC voltage source and a power field-effect transistor of a current limiter which are connected in series, and a second supply branch having a second DC voltage source. The power transistor has a current/voltage characteristic with a first inverse polarization area without current limitation, and a second conduction area with current limitation based on a current threshold. The power field-effect transistor is connected to the first voltage source with an inverse polarization when the voltage source of the first branch is operating normally.

Abstract: The invention relates to a power transistor for protecting, by limiting current, an electrical power supply, including one or more basic power vertical-junction field-effect transistors (602). Each basic power vertical junction field-effect transistor (602) includes at least one semiconductor depletion region (618, 620) forming a partially buried gate that defines a vertical channel (622) inside a first region (612). Each basic transistor includes a semiconductor depletion region (618, 620) forming an upper surface gate that is not buried, and defining a side channel inside a region (612) vertically adjacent to the first region.

Abstract: The present disclosure relates to a self-aligned metal mask assembly for selectively depositing thin films on microelectronic substrates and devices, comprising the following parts: a) an upper metal mask with the orifices or zones that define the patterns to be metalized, said mask having centring holes, b) a lower metal mask with orifices of the same size and shape as the substrates or devices to be metalized, and further auxiliary holes for centring the assembly, c) a piece or base provided with rods corresponding to the auxiliary holes, for centring the above parts, an upper piece or frame for securing and keeping the complete assembly aligned by means of screws and slight pressure. The assembly can in turn be secured to the sample-holder of the deposition machine.

Abstract: In the method, the following are placed in succession on a substrate: at least one conductive layer and at least one semiconductor power circuit, and metal connection tabs are fitted to the face of the semiconductor circuit facing away from the conductive layer by metallizing a metal film. Thereafter, at least one solder element is placed on each film obtained in this way, at least one conductive member is applied to the or each solder element on its side facing away from the metal film, and the or each solder element is caused to melt so as to secure the or each conductive member to the or each metal film.

Abstract: In the method, the following are placed in succession on a substrate: at least one conductive layer and at least one semiconductor power circuit, and metal connection tabs are fitted to the face of the semiconductor circuit facing away from the conductive layer by metallizing a metal film. Thereafter, at least one solder element is placed on each film obtained in this way, at least one conductive member is applied to the or each solder element on its side facing away from the metal film, and the or each solder element is caused to melt so as to secure the or each conductive member to the or each metal film.

Abstract: A current limiter component constituted by a semiconductor bar or wafer doped in four layers (P, N, P, N) between its anode and cathode. The doping characteristics and the dimensional characteristics of the bar are adjusted to obtain a characteristic current to voltage curve which initially increases as voltage and current increases in the manner of a diode followed by a part constituting a current limiting plateau wherein the plateau reflects that the current remains fixed until the voltage reaches a breakdown voltage.