Patents by Inventor Philippe Grosse
Philippe Grosse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11680870Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: GrantFiled: November 1, 2021Date of Patent: June 20, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
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Publication number: 20220183954Abstract: The present invention relates to an electrostatically sprayable cosmetic formulation having a sufficient sun protection factor, water resistance and caring effect, and which provides a sufficient, i.e. nearly full, coverage of the skin surface, when the formulation is applied on the surface of the skin by electrostatic spraying.Type: ApplicationFiled: December 10, 2021Publication date: June 16, 2022Applicant: IONIQ Skincare GmbH & Co. KGInventors: Charlotte VERDICCHI, Eva Harnisch, Annabella Lueck, Alfred Goehring, Thomas Jeltsch, Niklas Wemheuer, Philipp Fanous, Valentin Langen, Philipp Gross
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Patent number: 11187613Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: GrantFiled: April 30, 2020Date of Patent: November 30, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
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Patent number: 11131710Abstract: A photonic circuit testing device, including a photonic test chip including, on the side of a first surface of the chip: micropillars, each intended to be placed in contact with a corresponding electric connection pad of the photonic circuit; and first optical input/output ports, each intended to be optically coupled to a second corresponding optical input/output port of the photonic circuit.Type: GrantFiled: November 21, 2019Date of Patent: September 28, 2021Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Stéphane Bernabe, Philippe Grosse
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Patent number: 11099841Abstract: Annotations can be placed in source code to indicate properties for user-defined functions. A wide variety of properties can be implemented to provide information that can be leveraged when constructing a query execution plan for the user-defined function and associated core database relational operations. A flexible range of permitted partition arrangements can be specified via the annotations. Other supported properties include expected sorting and grouping arrangements, ensured post-conditions, and behavior of the user-defined function.Type: GrantFiled: January 23, 2019Date of Patent: August 24, 2021Assignee: SAP SEInventors: Philipp Grosse, Wolfgang Lehner, Norman May
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Publication number: 20200233661Abstract: Annotations can be placed in source code to indicate properties for user-defined functions. A wide variety of properties can be implemented to provide information that can be leveraged when constructing a query execution plan for the user-defined function and associated core database relational operations. A flexible range of permitted partition arrangements can be specified via the annotations. Other supported properties include expected sorting and grouping arrangements, ensured post-conditions, and behavior of the user-defined function.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Applicant: SAP SEInventors: Philipp Grosse, Wolfgang Lehner, Norman May
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Patent number: 10677684Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: GrantFiled: December 6, 2018Date of Patent: June 9, 2020Assignee: STMicroelectronics (Crolles 2) SASInventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
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Publication number: 20200174067Abstract: A photonic circuit testing device, including a photonic test chip including, on the side of a first surface of the chip: micropillars, each intended to be placed in contact with a corresponding electric connection pad of the photonic circuit; and first optical input/output ports, each intended to be optically coupled to a second corresponding optical input/output port of the photonic circuit.Type: ApplicationFiled: November 21, 2019Publication date: June 4, 2020Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Stéphane Bernabe, Philippe Grosse
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Patent number: 10528212Abstract: A method for determining a loading recommendation for a vehicle. The method involves object dimensions of objects with which the vehicle needs to be loaded being determined automatically using an optical capture apparatus, and an arrangement of the objects in a cargo space of the vehicle being determined on the basis of the object dimensions of the objects and a cargo space dimension of the cargo space. The arrangement of the objects in the cargo space is output as a loading recommendation.Type: GrantFiled: July 14, 2016Date of Patent: January 7, 2020Assignee: Volkswagen AGInventors: Philipp Gross, Lutz Oster
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Patent number: 10330865Abstract: A method of arranging a network of optical fiber ends opposite a corresponding network of waveguide ends of a semiconductor wafer displaceable with respect to each other in orthogonal directions X and Y, the method including: arranging the fibers so that the network ends have the same orientation and that the projection of the axis of each fiber on the wafer is parallel to direction Y; injecting, into one of the fibers, a light beam having a wavelength such that light is scattered from the fiber walls, locating the fiber axis, and displacing the fibers or the wafer in direction X to align a characteristic point in line with the projection of the fiber axis on the wafer.Type: GrantFiled: March 19, 2018Date of Patent: June 25, 2019Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Philippe Grosse, Jean-François Carpentier, Patrick Le Maitre
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Patent number: 10247890Abstract: A method of adjusting the parallelism of a surface of a block of optical fibers with a surface of a semiconductor chip or wafer laid on an XY table, including the steps of: a) providing a sensor rigidly attached to the XY table and a handling arm supporting the block, said surface facing the XY table; b) for each of three non-aligned points of the surface of the block, displacing with respect to each other the XY table and the block in the X and/or Y directions to place the sensor opposite the point, and estimating, with the sensor, the distance along the Z direction between the point and the sensor; and c) modifying the orientation of the block by means of the handling arm to provide the desired parallelism.Type: GrantFiled: March 9, 2018Date of Patent: April 2, 2019Assignee: Commissariat à l'Energie Atomique et aux Energies AlternativesInventor: Philippe Grosse
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Patent number: 10248688Abstract: Annotations can be placed in source code to indicate properties for user-defined functions. A wide variety of properties can be implemented to provide information that can be leveraged when constructing a query execution plan for the user-defined function and associated core database relational operations. A flexible range of permitted partition arrangements can be specified via the annotations. Other supported properties include expected sorting and grouping arrangements, ensured post-conditions, and behavior of the user-defined function.Type: GrantFiled: June 26, 2014Date of Patent: April 2, 2019Assignee: SAP SEInventors: Philipp Grosse, Wolfgang Lehner, Norman May
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Patent number: 10209442Abstract: Optical coupling of a photonic chip to an external device by use of a system with two lenses. The photonic chip comprises a light guide layer supported by a substrate and covered by an encapsulation layer, and a lens integrated into either the front face or the back face. The light guide layer includes a wave guide coupled to a surface grating coupler. An arrangement of one or several reflecting structures each on either the front face or the back face, is provided. This arrangement comprises a reflecting structure on the back face and is made so as to assure propagation of light between the surface grating coupler, and the lens along an optical path having at least one fold. The invention also covers the fabrication method of such a photonic chip.Type: GrantFiled: May 14, 2018Date of Patent: February 19, 2019Assignee: COMMISARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Sylvie Menezo, Stéphane Bernabe, Philippe Grosse
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Patent number: 10180373Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: GrantFiled: April 17, 2017Date of Patent: January 15, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
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Publication number: 20180335566Abstract: Optical coupling of a photonic chip to an external device by use of a system with two lenses. The photonic chip comprises a light guide layer supported by a substrate and covered by an encapsulation layer, and a lens integrated into either the front face or the back face. The light guide layer includes a wave guide coupled to a surface grating coupler. An arrangement of one or several reflecting structures each on either the front face or the back face, is provided. This arrangement comprises a reflecting structure on the back face and is made so as to assure propagation of light between the surface grating coupler, and the lens along an optical path having at least one fold. The invention also covers the fabrication method of such a photonic chip.Type: ApplicationFiled: May 14, 2018Publication date: November 22, 2018Inventors: Sylvie Menezo, Stéphane Bernabe, Philippe Grosse
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Publication number: 20180259727Abstract: A method of adjusting the parallelism of a surface of a block of optical fibers with a surface of a semiconductor chip or wafer laid on an XY table, including the steps of: a) providing a sensor rigidly attached to the XY table and a handling arm supporting the block, said surface facing the XY table; b) for each of three non-aligned points of the surface of the block, displacing with respect to each other the XY table and the block in the X and/or Y directions to place the sensor opposite the point, and estimating, with the sensor, the distance along the Z direction between the point and the sensor; and c) modifying the orientation of the block by means of the handling arm to provide the desired parallelism.Type: ApplicationFiled: March 9, 2018Publication date: September 13, 2018Inventor: Philippe Grosse
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Publication number: 20170307687Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: ApplicationFiled: April 17, 2017Publication date: October 26, 2017Applicant: STMicroelectronics (Crolles 2) SASInventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
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Publication number: 20170017502Abstract: A method for determining a loading recommendation for a vehicle. The method involves object dimensions of objects with which the vehicle needs to be loaded being determined automatically using an optical capture apparatus, and an arrangement of the objects in a cargo space of the vehicle being determined on the basis of the object dimensions of the objects and a cargo space dimension of the cargo space. The arrangement of the objects in the cargo space is output as a loading recommendation.Type: ApplicationFiled: July 14, 2016Publication date: January 19, 2017Inventors: Philipp GROSS, Lutz OSTER
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Patent number: 9454571Abstract: Technologies are disclosed for generating query execution plans optimized for parallel execution for programs having both core database relational functions and user-defined functions. A variety of optimization strategies can be employed to improve performance in a parallel execution scenarios. A flexible range of permitted partition arrangements can be specified as acceptable to parallelized instances of the user-defined function. The optimizer can leverage such information when constructing an optimized query execution plan. Partitioning arrangements or other properties can be leveraged to avoid additional or unnecessary processing.Type: GrantFiled: June 26, 2014Date of Patent: September 27, 2016Assignee: SAP SEInventors: Philipp Grosse, Wolfgang Lehner, Norman May
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Publication number: 20150379077Abstract: Technologies are disclosed for generating query execution plans optimized for parallel execution for programs having both core database relational functions and user-defined functions. A variety of optimization strategies can be employed to improve performance in a parallel execution scenarios. A flexible range of permitted partition arrangements can be specified as acceptable to parallelized instances of the user-defined function. The optimizer can leverage such information when constructing an optimized query execution plan. Partitioning arrangements or other properties can be leveraged to avoid additional or unnecessary processing.Type: ApplicationFiled: June 26, 2014Publication date: December 31, 2015Inventors: Philipp Grosse, Wolfgang Lehner, Norman May