Patents by Inventor Philippe Guasch

Philippe Guasch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9329671
    Abstract: Computer system, method and computer program product for scheduling IPC activities are disclosed. In one embodiment, the computer system includes first processor and second processors that communicate with each other via IPC activities. The second processor may operate in a first mode in which the second processor is able to process IPC activities, or a second mode in which the second processor does not process IPC activities. Processing apparatus associated with the first processor identifies which of the pending IPC activities for communicating from the first processor to the second processor are not real-time sensitive, and schedules the identified IPC activities for communicating from the first processor to the second processor by delaying some of the identified IPC activities to thereby group them together. The grouped IPC activities are scheduled for communicating to the second processor during a period in which the second processor is continuously in the first mode.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: May 3, 2016
    Assignee: Nvidia Corporation
    Inventors: Greg Heinrich, Philippe Guasch
  • Publication number: 20140215236
    Abstract: Computer system, method and computer program product for scheduling IPC activities are disclosed. In one embodiment, the computer system includes first processor and second processors that communicate with each other via IPC activities. The second processor may operate in a first mode in which the second processor is able to process IPC activities, or a second mode in which the second processor does not process IPC activities. Processing apparatus associated with the first processor identifies which of the pending IPC activities for communicating from the first processor to the second processor are not real-time sensitive, and schedules the identified IPC activities for communicating from the first processor to the second processor by delaying some of the identified IPC activities to thereby group them together. The grouped IPC activities are scheduled for communicating to the second processor during a period in which the second processor is continuously in the first mode.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Greg Heinrich, Philippe Guasch
  • Patent number: 8285979
    Abstract: A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: October 9, 2012
    Assignee: Icera Inc.
    Inventors: Alan Alexander, Philippe Guasch
  • Publication number: 20100095106
    Abstract: A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor.
    Type: Application
    Filed: October 15, 2009
    Publication date: April 15, 2010
    Applicant: ICERA Inc.
    Inventors: Alan Alexander, Philippe Guasch
  • Patent number: 7155538
    Abstract: An apparatus and method for providing adaptive error correction for a fax and/or modem over packet network session is disclosed. A gateway device configured in accordance with the present invention comprises a controller configured to receive a signal from its local client device and a signal processor coupled to said controller. The signal processor encodes the signal based on a level of error correction selected by the controller. The controller is configured to determine a type of signal communicated by the local client device from, and then select a level of error correction used by the signal processor to encode the signal based on the determined type of signal communicated by the local client device.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: December 26, 2006
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Norbert Rossello, Fabien Klein, Philippe Guasch