Abstract: Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: A very high speed low power receiver equalization system for non-return-to-zero transmission is disclosed. The equalizer comprises a three stage architecture, preferably controlled by three main parameters, the low frequency gain controlled through Rfb, the peaking frequency settled by the capacitor Cfpk, and the variable peak boosting Gpk which provides the equalizer transfer function and the optimum controls of the signal gain characteristic in order to compensate the ISI at the receiver input and consequently allow High speed, reliable links.

Abstract: A power clamp in a triple well is disclosed. A metal oxide semiconductor (MOS) varactor is used in a triggering circuit and is positioned in a first N type well. An N-channel field effect transistor is positioned in a P-type well. A P-channel field effect transistor is positioned in a second N-type well. The first N-type well is electrically isolated from the second N-type well, and electrically contacts the substrate of the power clamp.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Abstract: A transition detection, validation and memorization (TDVM) circuit detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. Then n over sampled signals are fed into the TDVM circuit which includes a first section for detecting the transition at the positions of two consecutive sampled signals according to a specific signal processing, a second section for validating the transition position, and a third section for memorizing the validated transition position and generating a control signal that is used to recover the data.

Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G0, . . . , Gn?1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G0, . . . , Gn?1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G0, . . . , Gn?1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin?) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Abstract: An improved data recovery circuit based on an oversampling technique wherein intersymbol interference (ISI) is compensated. A detection circuit is connected at the output of a conventional recovery circuit. The recovered data is applied to the detection circuit which includes flip-flops to memorize the previous state of the recovered data when no data transition is detected within a predefined number of clock periods. The detection circuit detects sequences of a predetermined number of consecutive identical bits which indicates the presence of ISI. It generates a feedback signal that is applied to the decision circuit and to the data sample selection circuit to shift the selection of a data sample of one position to compensate ISI.

Abstract: A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin−) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (SO, . . . , Sn−1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (C0, . . . , Cn−1) of a multiphase clock signal. A reliable over sampled signal is selected according to a select signal (G0. . . , Gn−1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing. In essence, the circuit comprises a plurality of n substantially identical logic blocks. The first logic block includes a latch receiving sampled signal So on its data input and the phase clock signal C0 on its clock input. Each other logic block, e.g. logic block i, further includes a multiplexer having two inputs, the first input is connected to the output of the latch of the preceding logic block and the second input receives sampled signal Si.

Abstract: There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position.

Abstract: A built-in self test system for testing a clock and data recovery circuit is disclosed. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.