Abstract: A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

Abstract: A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

Abstract: A memory element in an integrated circuit includes several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.

Abstract: A memory element in an integrated circuit including several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.