Abstract: The invention relates to a control method and system intended to reduce the common-mode current in a power converter which comprises a rectifier stage (1, 1?) connected to a number of input phases (R, S, T) and an inverter stage (2, 2?) connected to a number of output phases (U, V, W). On each switching period, the rectifier stage (1, 1?) and the inverter stage (2, 2?) are controlled in a synchronized manner so that a variation of potential applied to an input phase (R, S, T) always corresponds to a variation of potential of the same sign applied to an output phase (U, V, W).

Abstract: The invention relates to a control method and system intended to reduce the common-mode current in a power converter which comprises a rectifier stage (1, 1?) connected to a number of input phases (R, S, T) and an inverter stage (2, 2?) connected to a number of output phases (U, V, W). On each switching period, the rectifier stage (1, 1?) and the inverter stage (2, 2?) are controlled in a synchronized manner so that a variation of potential applied to an input phase (R, S, T) always corresponds to a variation of potential of the same sign applied to an output phase (U, V, W).

Abstract: A device controlling a JFET power electronic switch of normally ON type, including a main gate control circuit powered by a main power source for driving the gate of the JFET switch, a protection switching device that is switchable between two states, an auxiliary circuit controlling the switching device, and an auxiliary power source whose positive terminal is connected to the source of the JFET switch and whose negative terminal is connected to the gate of the JFET switch, bypassing the gate control circuit in one of the two positions of the switching device. The switching device can be an electromagnetic or electronic switch.

Abstract: The present invention relates to a parameterization method for a converter (1, 2) of the speed controller type, the said converter (1, 2) being connected to an electrical load (3) by means of an electrical cable (4) comprising at least two conductors, the method consisting in: generating common-mode current on the electrical cable (4) starting from a pulsed voltage comprising a first voltage edge (11, 13) and a second voltage edge (12, 14) delayed by a delay time (T) with respect to the first voltage edge (11, 13), measuring the common-mode current generated, making the delay time (T) between the two voltage edges (11, 12, 13, 14) generated vary, and determining an optimal delay time (T2) starting from a quantity (Ipeak, Ieff) representative of the common-mode current measured for the various values of the delay time (T).

Abstract: The present invention relates to a device for controlling a JFET power electronic switch (15) of the normally ON type, the control device comprising a main gate control circuit (30) powered by a main power source (11) for driving the gate of the JFET switch. The control device comprises a protection switching device (41,51) that is switchable between two states, an auxiliary circuit (40,50) for controlling the switching device, and an auxiliary power source (25) whose positive terminal is connected to the source of the JFET switch and whose negative terminal is connected to the gate of the JFET switch, bypassing said gate control circuit (30) in one of the two positions of the switching device. The switching device is an electromagnetic or electronic switch.

Abstract: The present invention relates to a parameterization method for a converter (1, 2) of the speed controller type, the said converter (1, 2) being connected to an electrical load (3) by means of an electrical cable (4) comprising at least two conductors, the method consisting in: generating common-mode current on the electrical cable (4) starting from a pulsed voltage comprising a first voltage edge (11, 13) and a second voltage edge (12, 14) delayed by a delay time (T) with respect to the first voltage edge (11, 13), measuring the common-mode current generated, making the delay time (T) between the two voltage edges (11, 12, 13, 14) generated vary, and determining an optimal delay time (T2) starting from a quantity (Ipeak, Ieff) representative of the common-mode current measured for the various values of the delay time (T).