Abstract: A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).

Abstract: The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The material of the cover layer can then easily be chosen such that it can be selectively etched relative to the silicon underneath. In addition, the cover layer can easily be selectively deposited on the relevant part of the surface because use can be made of an anisotropic deposition process. In such a process the cover layer is not deposited in the hollow and on the bottom of the hollow. It will be apparent that for the high-crystalline layer also other materials can be chosen such as SiGe having such low Ge contents that the SiGe cannot be etched selectively very well compared to the Silicon.

Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

Abstract: A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).