Patents by Inventor Philippe Piquet

Philippe Piquet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CROSSBAR STRUCTURE WITH MECHANISM FOR GENERATING CONSTANT OUTPUTS
    Publication number: 20120292667
    Abstract: Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: August 2, 2012
    Publication date: November 22, 2012
    Inventors: Olivier V. Lepape, Philippe Piquet
  • Crossbar structure with mechanism for generating constant outputs
    Patent number: 8245177
    Abstract: Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Meta Systems
    Inventors: Olivier V. Lepape, Philippe Piquet
  • Memory with five-transistor bit cells and associated control circuit
    Patent number: 8072796
    Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 6, 2011
    Assignee: Meta Systems
    Inventors: Jean Barbier, Olivier LePape, Philippe Piquet
  • CROSSBAR STRUCTURE WITH MECHANISM FOR GENERATING CONSTANT OUTPUTS
    Publication number: 20100115483
    Abstract: Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Applicant: M2000 SA.
    Inventors: Olivier V. Lepape, Philippe Piquet
  • MEMORY WITH FIVE-TRANSISTOR BIT CELLS AND ASSOCIATED CONTROL CIRCUIT
    Publication number: 20080055968
    Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 6, 2008
    Applicant: M2000 SA.
    Inventors: Jean Barbier, Olvier Lepape, Philippe Piquet
  • Memory with five-transistor bit cells and associated control circuit
    Patent number: 7307873
    Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: December 11, 2007
    Assignee: M2000 SA.
    Inventors: Jean Barbier, Olvier V. Lepape, Philippe Piquet
  • Memory with five-transistor bit cells and associated control circuit
    Publication number: 20070195583
    Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Inventors: Jean Barbier, Olvier Lepape, Philippe Piquet