Abstract: A data processing apparatus and method are provided for handling write access requests to shared memory. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with each processing unit having a cache associated therewith for storing a subset of the data for access by that processing unit. Cache coherency logic is provided that employs a cache coherency protocol to ensure data accessed by each processing unit is up-to-date. Each processing unit will issue a write access request when outputting a data value for storing in the shared memory, and when the write access request is of a type requiring both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic.

Abstract: A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer logic having a plurality of entries, each entry being selectively operable to store request information indicative of a previous request and to maintain associated cache information indicating whether a cache line in a cache is currently allocated for writing data values to an address associated with that request; and entry selection logic operable to determine which one of the plurality entries to allocate to store the request using the request information and the associated cache information of the plurality of entries to determine whether a cache line in the cache is currently allocated for writing the data value to the address in memory.

Abstract: There is disclosed a method, a cache controller and a data processing apparatus for allocating a data value to a cache way. The method comprises the steps of: (i) receiving a request to allocate the data value to an ‘n’-way set associative cache in which the data value may be allocated to a corresponding cache line of any one of the ‘n’-ways, where ‘n’ is an integer greater than 1; (ii) reviewing attribute information indicating whether the corresponding cache line of any of the ‘n’-ways is clean; and (iii) utilising the attribute information when executing a way allocation algorithm to provide an increased probability that the data value is allocated to a clean corresponding cache line. By allocating data value to the corresponding clean cache line there is no need to evict any data values prior to the allocation occurring, this obviates the need to power the eviction infrastructure and reduces eviction traffic over any interconnect.

Abstract: A cache controller and a method is provided. The cache controller comprises: request reception logic operable to receive a write request from a data processing apparatus to write a data item to memory; and cache access logic operable to determine whether a caching policy associated with the write request is write allocate, whether the write request would cause a cache miss to occur, whether the write request is one of a number of write requests which together would cause greater than a predetermined number of sequential data items to be allocated in the cache and, if so, the cache access logic is further operable to override the caching policy associated with the write request to non-write allocate.

Abstract: A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache.

Abstract: The present invention provides a data processing apparatus and method for handling cache accesses. The data processing apparatus comprises a processing unit operable to issue a series of access requests, each access request having associated therewith an address of a data value to be accessed. Further, the data processing apparatus has an n-way set associative cache memory operable to store data values for access by the processing unit, each way of the cache memory comprising a plurality of cache lines, and each cache line being operable to store a plurality of data values. The cache memory further comprises for each way a TAG storage for storing, for each cache line of that way, a corresponding TAG value.

Abstract: The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behaviour with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory.