Abstract: The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. It relates more specifically to a system for generation of a synchronization signal (PIPA, PIPB) and a clock signal (CLK_outA, CLK_outB) by a slave station (SA, SB) connected to a master station (SM) via a packet switching network. The master station (SM) is conformed to produce a master clock signal (CLKM) of frequency FM and a master synchronization signal (PIPM). The master synchronization signal (PIPM) is in phase with the master clock signal (SM). The slave station (SA, SB) comprises the primary synthesis means (SM1A, SM1B) producing a slave periodic signal TICKSA, TICKSB), the periodic signal (TICKSA, TICKSB) is in phase with the master clock signal (CLKM).

Abstract: The present invention relates to the architecture of a valve of liquid crystal elements with pixel memory for front or rear projector. The valve comprises elements arranged in rows and columns, each of the elements comprising a liquid crystal controlled by drive means so as to display video information relating to at least one image. According to the invention, one seeks to reduce the size of the drive means of the liquid crystals. Accordingly, capacitors and transistors of the drive means are shared in common between several elements of the valve. The video information intended to be displayed by each of the elements of the valve is coded as a common value shared by a group of at least two adjacent elements of the valve and a specific value before being transmitted to the valve.

Abstract: A device is operative to send packets in a packet communication network having at least two stations. According to an exemplary embodiment, the device operates by: extracting image pips on the basis of a synchronization signal; initializing a first counter on the basis of the the image pips; initializing a second counter according to zero-crossings of the first counter; sampling the second counter every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the network; sending packets containing the samples of the second counter in the network; receiving at least one phase deviation value ?? to be applied; and sending the at least one phase deviation value ?? in the network. The present invention also pertains to a device operative to receive packets in a packet communication network having at least two stations.

Abstract: The present invention pertains to a device able to send packets in a packet communication network comprising at least two stations, the said device comprising means for: -extracting image pips on the basis of a synchronization signal; -initializing a first counter on the basis of the said image pips; -initializing a second counter every “m” zero-crossings of the first counter; -sampling the second counter every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network; and -sending packets containing the samples in the network, characterized in that it comprises, furthermore, means for: receiving at least one phase deviation value ?? to be applied; -sending the phase deviation value ?? in the network. The present invention also pertains to a reception device able to receive packets in a packet communication network comprising at least two stations.

Abstract: The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. It relates more specifically to a system for generation of a synchronization signal (PIPA, PIPB) and a clock signal (CLK_outA, CLK_outB) by a slave station (SA, SB) connected to a master station (SM) via a packet switching network. The master station (SM) is conformed to produce a master clock signal (CLKM) of frequency FM and a master synchronization signal (PIPM). The master synchronization signal (PIPM) is in phase with the master clock signal (SM). The slave station (SA, SB) comprises the primary synthesis means (SM1A, SM1B) producing a slave periodic signal TICKSA, TICKSB), the periodic signal (TICKSA, TICKSB) is in phase with the master clock signal (CLKM).

Abstract: The present invention relates to the architecture of a valve of liquid crystal elements with pixel memory for front or rear projector. The valve comprises elements arranged in rows and columns, each of the elements comprising a liquid crystal controlled by drive means so as to display video information relating to at least one image. According to the invention, one seeks to reduce the size of the drive means of the liquid crystals. Accordingly, capacitors and transistors of the drive means are shared in common between several elements of the valve. The video information intended to be displayed by each of the elements of the valve is coded as a common value shared by a group of at least two adjacent elements of the valve and a specific value before being transmitted to the valve.