Patents by Inventor Philippe Therias

Philippe Therias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5260936
    Abstract: A store and forward apparatus includes a deserializer for deserializing received frames of data into a sequence of n-bit words. Each frame includes a header, a data field and a frame checking sequence (FCS) generated by a first telecommunication node. The apparatus includes a storage for storing the deserialized n-bit words, and a processor for addressing the storage and for generating n-bit words corresponding to a new header of the received frame. The apparatus also includes a serializer receiving the n-bit words from the storage for generating a new frame having a new header field and a new FCS to be transmitted to a second telecommunication node. The apparatus further includes a receiver for receiving a frame and computes a first partial FCS covering the frame's data field only and a storage for storing the first partial FCS. During forwarding, n-bit words to be transmitted are simultaneously received by the serializer and by an apparatus for computing a second partial FCS covering the data field only.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: November 9, 1993
    Assignee: International Business Machines Corp.
    Inventors: Gerard Bardet, Jean-Francois Le Pennec, Patrick Michel, Philippe Therias
  • Patent number: 5214771
    Abstract: Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor. The different memory and peripheral elements include first memory elements and first peripheral elements located in a first adapter pluggable into a base machine and second memory elements and second peripheral elements located into a second adapter pluggable into the base machine. The processor further addresses third memory elements and third peripheral elements located in the base machine. The first and second memory elements include code which has a determined type and a determined level of release.
    Type: Grant
    Filed: September 1, 1989
    Date of Patent: May 25, 1993
    Assignee: International Business Machines Corp.
    Inventors: Jean-Louis Clara, Philippe Jachimczyk, Jean-Freancois Le Pennec, Louis Massiera, Philippe Therias
  • Patent number: 5043989
    Abstract: A terminal adapter for a telecommunication network having a receiver for multiple HDLC communication channels. The receiver includes a BCC calculator for computing and checking the validity of a received HDLC CNM frame. The terminal adapter further includes a device for detecting the reception of a specific CNM header included in a CNM frame on any of the HDLC communication channels and responsive to the detection for setting the BCC calculator to a predefined state. The latter state corresponds to the state of the BCC calculator after a computation of BCC for the specific CNM header. Therefore the BCC calculator can proceed with computation of said BCC for the CNM frame.
    Type: Grant
    Filed: September 1, 1989
    Date of Patent: August 27, 1991
    Assignee: International Business Machines Corp.
    Inventors: Philippe Dalmas, Daniel Esteban, Jean-Francois Le Pennec, Patrick Michel, Philippe Therias