Patents by Inventor Philippe Vereecken

Philippe Vereecken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060086616
    Abstract: A plating apparatus can securely carry out a flattening plating of a substrate to form a plated film having a flat surface without using a costly mechanism, and without applying an extra plating to the substrate. The plating apparatus includes a substrate holder; a cathode section having a seal member for watertightly sealing a peripheral portion of the substrate, and a cathode electrode for supplying an electric current to the substrate; an anode disposed in a position facing the surface of the substrate; a porous member disposed between the anode and the surface of the substrate; a constant-voltage control section for controlling a voltage applied between the cathode electrode and the anode at a constant value; and a current monitor section for monitoring an electric current flowing between the cathode electrode and the anode, and feeding back a detection signal to the constant-voltage control section.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 27, 2006
    Inventors: Keiichi Kurashina, Mizuki Nagai, Satoru Yamamoto, Hiroyuki Kanda, Koji Mishima, Shinya Morisawa, Junji Kunisawa, Kunihito Ide, Hidenao Suzuki, Emanuel Cooper, Philippe Vereecken, Brett Baker-O' Neal, Hariklia Deligianni
  • Publication number: 20060081885
    Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 20, 2006
    Applicant: International Business Machines Corporation
    Inventors: Katherine Saenger, Cyril Cabral, Hariklia Deligianni, Panayotis Andricacos, Caliopi Andricacos, Philippe Vereecken, Emanuel Cooper
  • Publication number: 20060076685
    Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
    Type: Application
    Filed: November 3, 2005
    Publication date: April 13, 2006
    Applicant: International Business Machines
    Inventors: Panayotis Andricacos, Shyng-Tsong Chen, John Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe Vereecken
  • Publication number: 20050241946
    Abstract: A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.
    Type: Application
    Filed: December 21, 2004
    Publication date: November 3, 2005
    Inventors: Mizuki Nagai, Hiroyuki Kanda, Keiichi Kurashina, Satoru Yamamoto, Ryoichi Kimizuka, Hariklia Deligianni, Brett Baker, Keith Kwietniak, Panayotis Andricacos, Philippe Vereecken
  • Publication number: 20050199502
    Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
    Type: Application
    Filed: May 6, 2005
    Publication date: September 15, 2005
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Horkans, Keith Kwietniak, Michael Lane, Sandra Malhotra, Fenton McFeely, Conal Murray, Kenneth Rodbell, Philippe Vereecken
  • Publication number: 20050095852
    Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 5, 2005
    Applicant: International Business Machines
    Inventors: Katherine Saenger, Cyril Cabral, Emanuel Cooper, Hariklia Deligianni, Panayotis Andricacos, Philippe Vereecken
  • Publication number: 20050006242
    Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 13, 2005
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Dean Chung, Hariklia Deligianni, James Fluegel, Keith Kwietniak, Peter Locke, Darryl Restaino, Soon-Cheon Seo, Philippe Vereecken, Erick Walton
  • Publication number: 20050001325
    Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 6, 2005
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Shyng-Tsong Chen, John Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe Vereecken