Abstract: A secure cryptographic logic arrangement immediately halts the processing of its internal processors upon detection of a single fault. The cryptographic logic arrangement has an arithmetic logic unit, permuter, and a non-linear combiner. A total self-checking controller monitors each of the arithmetic logic unit, permuter, and non-linear combiner to determine whether a fault has occurred in any one of its internal processors. The total self-checking controller employs a scheme of transmitting a pseudorandom signal to each of the internal processors and compares a phase of the pseudorandom signal received back from each of the internal processors to determine whether a fault exists.