Patents by Inventor Phillip A. Rasmussen
Phillip A. Rasmussen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954342Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.Type: GrantFiled: October 19, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventors: Wolfgang Anton Spirkl, Phillip A. Rasmussen, Thomas Hein
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Patent number: 11815554Abstract: A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the last passing point, write data within the logic circuit of the tester identifying the last passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.Type: GrantFiled: January 20, 2021Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventors: Phillip A. Rasmussen, Christopher D. Gagliano
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Publication number: 20230057441Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.Type: ApplicationFiled: October 19, 2022Publication date: February 23, 2023Inventors: Wolfgang Anton Spirkl, Phillip A. Rasmussen, Thomas Hein
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Patent number: 11561876Abstract: Methods, systems, and devices for a fail compare procedure are described. An apparatus may include a host device coupled with a memory device. An application specific integrated circuit (ASIC) associated with the host device (e.g., included in, coupled with) may include a set of comparators that output first bit information that includes respective states of at least two bits of data read from the memory device. The host device may compare (e.g., at the ASIC) the first bit information to second bit information that includes respective expected states of the at least two bits. Based on the comparison, the host device may determine whether a state of at least one bit of the first bit information is different than a state of a corresponding bit of the second bit information, and may output one or more signals including indications of a fail to a counter of the ASIC.Type: GrantFiled: January 19, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventor: Phillip A. Rasmussen
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Patent number: 11500561Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.Type: GrantFiled: May 3, 2021Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventors: Wolfgang Anton Spirkl, Phillip A. Rasmussen, Thomas Hein
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Publication number: 20220350512Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Inventors: Wolfgang Anton Spirkl, Phillip A. Rasmussen, Thomas Hein
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Publication number: 20220229751Abstract: Methods, systems, and devices for a fail compare procedure are described. An apparatus may include a host device coupled with a memory device. An application specific integrated circuit (ASIC) associated with the host device (e.g., included in, coupled with) may include a set of comparators that output first bit information that includes respective states of at least two bits of data read from the memory device. The host device may compare (e.g., at the ASIC) the first bit information to second bit information that includes respective expected states of the at least two bits. Based on the comparison, the host device may determine whether a state of at least one bit of the first bit information is different than a state of a corresponding bit of the second bit information, and may output one or more signals including indications of a fail to a counter of the ASIC.Type: ApplicationFiled: January 19, 2021Publication date: July 21, 2022Inventor: Phillip A. Rasmussen
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Publication number: 20220229108Abstract: A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the second passing point, write data within the logic circuit of the tester identifying the second passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.Type: ApplicationFiled: January 20, 2021Publication date: July 21, 2022Inventors: Phillip A. Rasmussen, Christopher D. Gagliano
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Patent number: 8607111Abstract: An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.Type: GrantFiled: August 30, 2006Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Phillip Rasmussen, Charles Snodgrass
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Publication number: 20080082886Abstract: An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.Type: ApplicationFiled: August 30, 2006Publication date: April 3, 2008Inventors: Phillip Rasmussen, Charles Snodgrass
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Patent number: 6522161Abstract: A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i.e., the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.Type: GrantFiled: July 5, 2001Date of Patent: February 18, 2003Assignee: Micron Technology, Inc.Inventors: Aron T. Lunde, Phillip A. Rasmussen
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Publication number: 20020049941Abstract: A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i.e., the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.Type: ApplicationFiled: July 5, 2001Publication date: April 25, 2002Inventors: Aron T. Lunde, Phillip A. Rasmussen
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Patent number: 6275058Abstract: A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i.e., the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.Type: GrantFiled: January 26, 1999Date of Patent: August 14, 2001Assignee: Micron Technology, Inc.Inventors: Aron T. Lunde, Phillip A. Rasmussen