Patents by Inventor Phillip Burlison

Phillip Burlison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090132870
    Abstract: A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.
    Type: Application
    Filed: November 15, 2007
    Publication date: May 21, 2009
    Applicant: INOVYS CORPORATION
    Inventors: PHILLIP BURLISON, MEI-MEI SU, JOHN FREDIANI
  • Patent number: 7191368
    Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: March 13, 2007
    Assignee: LTX Corporation
    Inventors: Donald V. Organ, Kenneth J. Lanier, Roger W. Blethen, H. Neil Kelly, Michael G. Davis, Jeffrey H. Perkins, Tommie Berry, Phillip Burlison, Mark Deome, Christopher J. Hannaford, Edward J. Terrenzi, David Menis, David W. Curry, Eric Rosenfeld
  • Patent number: 7092837
    Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 15, 2006
    Assignee: LTX Corporation
    Inventors: Kenneth J. Lanier, Roger W. Blethen, H. Neil Kelly, Michael G. Davis, Jeffrey H. Perkins, Tommie Berry, Phillip Burlison, Mark Deome, Christopher J. Hannaford, Edward J. Terrenzi, David Menis, David W. Curry, Eric Rosenfeld
  • Patent number: 6675339
    Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: January 6, 2004
    Assignee: LTX Corporation
    Inventors: Kenneth J. Lanier, Roger W. Blethen, H. Neil Kelly, Michael G. Davis, Jeffrey H. Perkins, Tommie Berry, Phillip Burlison, Mark Deome, Christopher J. Hannaford, Edward J. Terrenzi, David Menis, David W. Curry, Eric Rosenfeld
  • Patent number: 6449741
    Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: September 10, 2002
    Assignee: LTX Corporation
    Inventors: Donald V. Organ, Kenneth J. Lanier, Roger W. Blethen, H. Neil Kelly, Michael G. Davis, Jeffrey H. Perkins, Tommie Berry, Phillip Burlison, Mark Deome, Christopher J. Hannaford, Edward J. Terrenzi, David Menis, David W. Curry, Eric Rosenfeld