Patents by Inventor Phillip C. Celaya

Phillip C. Celaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lead-free integrated circuit package structure
    Patent number: 7180170
    Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: February 20, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
  • Method of making a lead-free integrated circuit package
    Patent number: 6889429
    Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: May 10, 2005
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
  • Integrated circuit package and method
    Publication number: 20020134582
    Abstract: An integrated circuit package(60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
    Type: Application
    Filed: March 26, 2001
    Publication date: September 26, 2002
    Applicant: Semiconductor Components Industries, LLC.
    Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
  • Microelectronic package including a polymer encapsulated die
    Patent number: 6093972
    Abstract: A microelectronic package (10) is formed and includes an integrated circuit die (12) attached to a substrate (14) by a plurality of solder bump interconnections (16) to form a preassembly (18). The integrated circuit die (12) has an active face (20) that faces the substrate (14) and is spaced apart therefrom by a gap (22). The integrated circuit die (12) also includes a back face (24) opposite the active face (20). The substrate (14) includes a die attach region (26) and a surrounding region (28) about the integrated circuit die (12). The solder bump interconnections (16) extend across the gap (22) and connect the integrated circuit die (12) and the substrate (14). A mold (30) is disposed about the preassembly (18) such that the mold (30) cooperates with the substrate (14) to define a mold cavity (32) that encloses the integrated circuit die (12).
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: July 25, 2000
    Assignee: Motorola, Inc.
    Inventors: Francis J. Carney, George Amos Carson, Phillip C. Celaya, Harry Fuerhaupter, Frank Tim Jones, Donald H. Klosterman, Cynthia M. Melton, James Howard Knapp, Keith E. Nelson
  • Microelectronic package including a polymer encapsulated die, and method for forming same
    Patent number: 5895229
    Abstract: A microelectronic package (10) is formed and includes an integrated circuit die (12) attached to a substrate (14) by a plurality of solder bump interconnections (16) to form a preassembly (18). The integrated circuit die (12) has an active face (20) that faces the substrate (14) and is spaced apart therefrom by a gap (22). The integrated circuit die (12) also includes a back face (24) opposite the active face (20). The substrate (14) includes a die attach region (26) and a surrounding region (28) about the integrated circuit die (12). The solder bump interconnections (16) extend across the gap (22) and connect the integrated circuit die (12) and the substrate (14). A mold (30) is disposed about the preassembly (18) such that the mold (30) cooperates with the substrate (14) to define a mold cavity (32) that encloses the integrated circuit die (12).
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: April 20, 1999
    Assignee: Motorola, Inc.
    Inventors: Francis J. Carney, George Amos Carson, Phillip C. Celaya, Harry Fuerhaupter, Frank Tim Jones, Donald H. Klosterman, Cynthia M. Melton, James Howard Knapp, Keith E. Nelson
  • Electronic component assembly having an encapsulation material and method of forming the same
    Patent number: 5808873
    Abstract: An electronic component assembly (10) is formed by mounting an electronic component (31) to a substrate (11). An encapsulating material (33) is used to protect the electronic component (31) from environmental hazards. The encapsulating material (33) is formed by dispensing an encapsulating fluid over the electronic component (31). A trench (36) is formed in a masking layer (21) on a substrate (11) to stop the flow of the encapsulating fluid. The trench (36) provides an edge (35) which acts as a discontinuity in the surface (23) of the masking layer (21). This discontinuity is sufficient to control the flow of the encapsulating fluid until the encapsulating fluid is cured to form the encapsulating material (33).
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: September 15, 1998
    Assignee: Motorola, Inc.
    Inventors: Phillip C. Celaya, John R. Kerr