Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire located in an interconnect layer of said semiconductor device, the at least one wire having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.

Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire (135) located in an interconnect layer of said semiconductor device, the at least one wire (135) having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire (135?) is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.

Abstract: Holographic test structures on a semiconductor wafer are used to provide real-time analysis of upstream fabrication processing parameters. The test structures comprise reflective segments within multiple cells on the test structure. The size and placement of the reflective segments within the cells are determined by diffraction theory in such a way that a desired image is projected from the test structure. The intensity, sharpness, and shape of the image is used as a direct measure of the upstream fabrication process parameters.