Patents by Inventor Phillip Czeslaw Jozwiak
Phillip Czeslaw Jozwiak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7414273Abstract: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.Type: GrantFiled: July 7, 2005Date of Patent: August 19, 2008Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Russell Mohn, Cong-Son Trinh, Phillip Czeslaw Jozwiak, John Armer, Markus Paul Josef Mergens
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Patent number: 7372681Abstract: An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fingered MOS transistor, each finger respectively adapted for coupling between an I/O pad and a first supply line of the IC. An ESD detector is coupled to the I/O pad via a first terminal, and a second terminal is adapted for coupling to a second supply line potential of the IC. A parasitic capacitance is formed between the second supply line potential of the IC and the first supply line potential. A transfer circuit is coupled to a third terminal of the ESD detector and is adapted for biasing at least one gate respectively associated with at least one finger of the multi-fingered MOS transistor.Type: GrantFiled: April 13, 2005Date of Patent: May 13, 2008Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: John Armer, Markus Paul Josef Mergens, Phillip Czeslaw Jozwiak, Cornelius Christian Russ
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Patent number: 7233467Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.Type: GrantFiled: March 23, 2005Date of Patent: June 19, 2007Assignees: Sarnoff Corporation, Sarnoff Europe BVBAInventors: Markus Paul Josef Mergens, Frederic Marie Dominique De Ranter, Benjamin Van Camp, Koen Gerard Maria Verhaege, Phillip Czeslaw Jozwiak, John Armer, Bart Keppens
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Patent number: 7064393Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.Type: GrantFiled: February 20, 2004Date of Patent: June 20, 2006Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Markus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Koen Gerard Maria Verhaege, Phillip Czeslaw Jozwiak
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Patent number: 7005708Abstract: An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.Type: GrantFiled: May 12, 2003Date of Patent: February 28, 2006Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Markus Paul Josef Mergens, Koen Gerard Maria Verhaege, Cornelius Christian Russ, John Armer, Phillip Czeslaw Jozwiak, Bart Keppens
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Patent number: 6909149Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages.Type: GrantFiled: April 15, 2004Date of Patent: June 21, 2005Assignees: Sarnoff Corporation, Sarnoff Europe BVBAInventors: Cornelius Christian Russ, Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, Cong-Son Trinh, Russell Mohn, Koen Gerard Maria Verhaege
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Patent number: 6898062Abstract: An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.Type: GrantFiled: April 12, 2004Date of Patent: May 24, 2005Assignee: Sarnoff CorporationInventors: Cornelius Christian Russ, John Armer, Markus Paul Josef Mergens, Phillip Czeslaw Jozwiak
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Publication number: 20040207021Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages.Type: ApplicationFiled: April 15, 2004Publication date: October 21, 2004Inventors: Cornelius Christian Russ, Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, Cong-Son Trinh, Russell Mohn, Koen Gerard Maria Verhaege
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Patent number: 6803633Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.Type: GrantFiled: March 15, 2002Date of Patent: October 12, 2004Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Markus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Koen Gerard Maria Verhaege, Phillip Czeslaw Jozwiak
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Publication number: 20040190209Abstract: Apparatus for generating an additional voltage drop to reduce the dangerously high voltage drop across an ESD-sensitive ultra-thin gate oxide of a MOS input device. The apparatus are designed to minimally interfere with the circuit requirements for normal operation. Specifically, The MOS input device is coupled between a pad and the logic core circuitry of the IC. In one embodiment, a voltage-drop element, such as a resistive element, inductor, or pass-gate MOS device, is coupled between the source of the MOS input device and a voltage line. Alternatively, the voltage-drop element may be coupled to the bulk, gate, and/or drain of the MOS input device. In another embodiment, the voltage-drop device may be an active device, which pumps up the potential at least one of the source, bulk, or drain regions of the input device from the ESD clamp.Type: ApplicationFiled: March 29, 2004Publication date: September 30, 2004Applicant: Sarnoff CorporationInventors: Phillip Czeslaw Jozwiak, John Armer, Markus Paul Josef Mergens, Christian Cornelius Russ
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Publication number: 20040188776Abstract: An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger Includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.Type: ApplicationFiled: April 12, 2004Publication date: September 30, 2004Inventors: Cornelius Christian Russ, John Armer, Markus Paul Josef Mergens, Phillip Czeslaw Jozwiak
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Publication number: 20040164354Abstract: An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.Type: ApplicationFiled: May 12, 2003Publication date: August 26, 2004Applicant: Sarnoff CorporationInventors: Markus Paul Josef Mergens, Koen Gerard Maria Verhaege, Cornelius Christian Russ, John Armer, Phillip Czeslaw Jozwiak, Bart Keppens
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Publication number: 20040164356Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.Type: ApplicationFiled: February 20, 2004Publication date: August 26, 2004Applicant: Sarnoff CorporationInventors: Markus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Koen Gerard Maria Verhaege, Phillip Czeslaw Jozwiak
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Patent number: 6770918Abstract: An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N+ doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.Type: GrantFiled: September 10, 2002Date of Patent: August 3, 2004Assignee: Sarnoff CorporationInventors: Cornelius Christian Russ, John Armer, Markus Paul Josef Mergens, Phillip Czeslaw Jozwiak
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Patent number: 6583972Abstract: A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.Type: GrantFiled: June 14, 2001Date of Patent: June 24, 2003Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Koen Gerard Maria Verhaege, Markus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Phillip Czeslaw Jozwiak
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Publication number: 20030047750Abstract: An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N+ doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.Type: ApplicationFiled: September 10, 2002Publication date: March 13, 2003Applicant: Sarnoff CorporationInventors: Cornelius Christian Russ, John Armer, Markus Paul Josef Mergens, Phillip Czeslaw Jozwiak
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Publication number: 20020153571Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.Type: ApplicationFiled: March 15, 2002Publication date: October 24, 2002Inventors: Markus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Koen Gerard Maria Verhaege, Phillip Czeslaw Jozwiak
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Publication number: 20020033507Abstract: A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.Type: ApplicationFiled: June 14, 2001Publication date: March 21, 2002Inventors: Koen Gerard Maria Verhaege, Markus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Phillip Czeslaw Jozwiak