Patents by Inventor Phillip E. Krueger
Phillip E. Krueger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9852073Abstract: In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the cache, write the data to a second portion of the cache, and delete the data from the second portion of the cache when the data in the first portion of the cache is flushed.Type: GrantFiled: August 7, 2012Date of Patent: December 26, 2017Assignee: DELL PRODUCTS L.P.Inventors: Scott David Peterson, Phillip E. Krueger
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Patent number: 9549037Abstract: In one embodiment, a computing system includes a cache including one or more memories and a cache manager. The cache manager is able to determine an amount of accessible data for a portion of the cache associated with the cache manager; compare the amount of accessible data to a threshold value; determine, for one or more clients associated with the cache manager, an amount of releasable data if the amount of accessible data exceeds the threshold value; communicate, to one or more clients associated with the cache manager, the amount of releasable data for the client; receive from one or more clients associated with the cache manager information associated with data released by the one or more clients; and determine an amount of data released by the one or more clients associated with the cache manager.Type: GrantFiled: August 7, 2012Date of Patent: January 17, 2017Assignee: DELL PRODUCTS L.P.Inventors: Phillip E. Krueger, Christopher August Shaffer
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Patent number: 9495301Abstract: In one embodiment, a computing system includes a cache having one or more memories, a cache journal operable to store data associated with one or more portions of the cache, and a configuration manager operable to access the cache and the cache journal. The configuration manager is operable to determine whether the cache journal includes data associated with a first portion of the cache, and to create, in the cache journal, data associated with the first portion of the cache if the cache journal does not yet comprise data associated with the first portion of the cache. The configuration manager is also operable to determine whether the first portion of the cache is valid for use, and to communicate with a memory manager associated with the first portion of the cache regarding whether the first portion of the cache is valid for use.Type: GrantFiled: August 7, 2012Date of Patent: November 15, 2016Assignee: DELL PRODUCTS L.P.Inventors: Jason Philip Gross, Ranjit Pandit, Scott David Peterson, Phillip E. Krueger, Christopher Mark Greiveldinger
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Publication number: 20160239417Abstract: In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.Type: ApplicationFiled: April 22, 2016Publication date: August 18, 2016Inventors: Scott David Peterson, Christopher August Shaffer, Phillip E. Krueger
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Patent number: 9367480Abstract: In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.Type: GrantFiled: August 7, 2012Date of Patent: June 14, 2016Assignee: Dell Products L.P.Inventors: Scott David Peterson, Christopher August Shaffer, Phillip E. Krueger
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Publication number: 20140047193Abstract: In one embodiment, a computing system includes a cache having one or more memories, a cache journal operable to store data associated with one or more portions of the cache, and a configuration manager operable to access the cache and the cache journal. The configuration manager is operable to determine whether the cache journal includes data associated with a first portion of the cache, and to create, in the cache journal, data associated with the first portion of the cache if the cache journal does not yet comprise data associated with the first portion of the cache. The configuration manager is also operable to determine whether the first portion of the cache is valid for use, and to communicate with a memory manager associated with the first portion of the cache regarding whether the first portion of the cache is valid for use.Type: ApplicationFiled: August 7, 2012Publication date: February 13, 2014Applicant: DELL PRODUCTS L.P.Inventors: Jason Philip Gross, Ranjit Pandit, Scott David Peterson, Phillip E. Krueger, Christopher Mark Greiveldinger
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Publication number: 20140047062Abstract: In one embodiment, a computing system includes a cache including one or more memories and a cache manager. The cache manager is able to determine an amount of accessible data for a portion of the cache associated with the cache manager; compare the amount of accessible data to a threshold value; determine, for one or more clients associated with the cache manager, an amount of releasable data if the amount of accessible data exceeds the threshold value; communicate, to one or more clients associated with the cache manager, the amount of releasable data for the client; receive from one or more clients associated with the cache manager information associated with data released by the one or more clients; and determine an amount of data released by the one or more clients associated with the cache manager.Type: ApplicationFiled: August 7, 2012Publication date: February 13, 2014Applicant: DELL PRODUCTS L.P.Inventors: Phillip E. Krueger, Christopher August Shaffer
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Publication number: 20140047185Abstract: In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the cache, write the data to a second portion of the cache, and delete the data from the second portion of the cache when the data in the first portion of the cache is flushed.Type: ApplicationFiled: August 7, 2012Publication date: February 13, 2014Applicant: DELL PRODUCTS L.P.Inventors: Scott David Peterson, Phillip E. Krueger
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Publication number: 20140047181Abstract: In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.Type: ApplicationFiled: August 7, 2012Publication date: February 13, 2014Applicant: DELL PRODUCTS L.P.Inventors: Scott David Peterson, Christopher August Shaffer, Phillip E. Krueger
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Patent number: 7472233Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.Type: GrantFiled: April 30, 2004Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Paul E. McKenney, Phillip E. Krueger, Stuart A. Friedberg, Brent A. Kingsbury
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Patent number: 7149853Abstract: A system and method are disclosed for providing a synchronization mechanism for access to shared information. According to an embodiment of the present invention, a lock with more than one part can be obtained or leased by writing to the first part, writing to the second part, reading the first part to determine whether the first part reads what was written to it, and obtaining the lock if what is read is the same as what was written.Type: GrantFiled: September 20, 2002Date of Patent: December 12, 2006Assignee: PolyServe, Inc.Inventor: Phillip E. Krueger
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Publication number: 20040205304Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.Type: ApplicationFiled: April 30, 2004Publication date: October 14, 2004Inventors: Paul E. McKenney, Phillip E. Krueger, Stuart A. Friedberg, Brent A. Kingsbury
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Patent number: 6785888Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.Type: GrantFiled: February 24, 1998Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Paul E. McKenney, Phillip E. Krueger, Stuart A. Friedberg, Brent A. Kingsbury
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Patent number: 6615316Abstract: A method and computer system for estimating cache warmth for thread schedulers in a processor of a multiprocessor system. A mathematical model based upon a Markov Model of queuing theory is used to determine flow probability. The method incorporates data received from cache counters to measure cache hits, cache misses, cache invalidations and cache roll-outs. Based upon the Model and the data received from the counters and the assumption that cache decays exponentially, a nominal lifetime of a cache line is computed and the state of the system is manipulated in accordance with the computed lifetime of the cache line. The method may be applied to either a two way LRU cache or a four way LRU cache for computing an average lifetime of a cache line. Accordingly, cache affinity and thread migration decisions are enhanced thereby providing an efficient method of operating a computer system.Type: GrantFiled: November 16, 2000Date of Patent: September 2, 2003Assignee: International Business Machines, CorporationInventors: Paul E. McKenney, Phillip E. Krueger
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Publication number: 20030065896Abstract: A system and method are disclosed for providing a synchronization mechanism for access to shared information. According to an embodiment of the present invention, a lock with more than one part can be obtained or leased by writing to the first part, writing to the second part, reading the first part to determine whether the first part reads what was written to it, and obtaining the lock if what is read is the same as what was written.Type: ApplicationFiled: September 20, 2002Publication date: April 3, 2003Applicant: PolyServe, Inc.Inventor: Phillip E. Krueger
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Patent number: 6505286Abstract: A method for a user process to specify a policy for allocating pages of physical memory on the nodes of a multinode multiprocessor computer system. Through means such as a system call, an application program can specify to the operating system that physical pages of memory for an application-specified portion of virtual address space are to be physically allocated upon a specified set of nodes, subject to the additional selection criteria that the pages are to be allocated at first reference upon: 1) the node upon which the reference first occurs; 2) the node which has the most free memory, or 3) that the pages should be evenly distributed across the indicated set of nodes. In effect, the operating system remembers the specified allocation policy and node set from which the physical pages can be subsequently allocated as established by a system call. Subsequent use of the virtual address space for which the allocation policy is defined results in the memory being allocated accordingly.Type: GrantFiled: September 22, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Brent A. Kingsbury, Corene Casper, Phillip E. Krueger, Paul E. McKenney
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Patent number: 6205528Abstract: A method for a user process to specify a policy for allocating pages of physical memory on the nodes of a multinode multiprocessor computer system. Through means such as a system call, an application program can specify to the operating system that physical pages of memory for an application-specified portion of virtual address space are to be physically allocated upon a specified set of nodes, subject to the additional selection criteria that the pages are to be allocated at first reference upon: 1) the node upon which the reference first occurs; 2) the node which has the most free memory, or 3) that the pages should be evenly distributed across the indicated set of nodes. In effect, the operating system remembers the specified allocation policy and node set from which the physical pages can be subsequently allocated, as established by a system call. Subsequent use of the virtual address space for which the allocation policy is defined results in the memory being allocated accordingly.Type: GrantFiled: August 29, 1997Date of Patent: March 20, 2001Assignee: International Business Machines CorporationInventors: Brent A. Kingsbury, Corene Casper, Phillip E. Krueger, Paul E. McKenney
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Patent number: 6049853Abstract: For a multiprocessor computer having shared memory distributed across multiple nodes, a method and system for dynamically replicating data such as program text stored in memory on a first node to memory on a second node for use by a process executing on the second node. In response to a page fault generated by the process in accessing data, a determination is made whether the data is present in the memory of another node. If so, memory is allocated on the process's node for the data, and the needed data is copied from the other node to the process's node. The process's page table entry for the missing data is then modified to contain the physical address of the allocated memory, where the data is now stored. The method is implemented in a preferred embodiment by using novel data structures linked to the data structures that are typically created when a file is mapped to a process's virtual address space.Type: GrantFiled: August 29, 1997Date of Patent: April 11, 2000Assignee: Sequent Computer Systems, Inc.Inventors: Brent A. Kingsbury, Corene Casper, Phillip E. Krueger