Patents by Inventor Phillip E. Nevius

Phillip E. Nevius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic remapping of cache lines
    Patent number: 9424195
    Abstract: A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 23, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Johnsy Kanjirapallil John, Phillip E. Nevius, Robert G. Gelinas
  • Detecting and correcting hard errors in a memory array
    Patent number: 9189326
    Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: November 17, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Johnsy Kanjirapallil John, Robert Gelinas, Vilas K. Sridharan, Phillip E. Nevius
  • DYNAMIC REMAPPING OF CACHE LINES
    Publication number: 20150293854
    Abstract: A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 15, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Johnsy Kanjirapallil John, Phillip E. Nevius, Robert G. Gelinas
  • DETECTING AND CORRECTING HARD ERRORS IN A MEMORY ARRAY
    Publication number: 20150100848
    Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Johnsy Kanjirapallil John, Robert Gelinas, Vilas K. Sridharan, Phillip E. Nevius