Patents by Inventor Phillip G. Hays
Phillip G. Hays has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11829755Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.Type: GrantFiled: August 1, 2022Date of Patent: November 28, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
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Patent number: 11829301Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. A first operand formatted in a universal number or posit format can be received by a first buffer resident on acceleration circuitry. A second operand formatted in a universal number or posit format can be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both can be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both can be received by a third buffer resident on the acceleration circuitry.Type: GrantFiled: April 24, 2020Date of Patent: November 28, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
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Publication number: 20220382545Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.Type: ApplicationFiled: August 1, 2022Publication date: December 1, 2022Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
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Patent number: 11403096Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.Type: GrantFiled: May 11, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
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Publication number: 20210349714Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
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Publication number: 20210334219Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. A first operand formatted in a universal number or posit format can be received by a first buffer resident on acceleration circuitry. A second operand formatted in a universal number or posit format can be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both can be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both can be received by a third buffer resident on the acceleration circuitry.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
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Patent number: 11012593Abstract: A fault tolerant display displays safety information on a display shared with an infotainment system even if the processor or software of the infotainment system is unresponsive. The display can be a streaming video from a rear view camera mounted on a vehicle. The safety displayed can be triggered by placing the vehicle in reverse. Failure of the infotainment software and/or processor can be detected by a policy enforcing module that switches to a backup display that streams video directly from the camera in the event of failure of the infotainment processor.Type: GrantFiled: June 14, 2018Date of Patent: May 18, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Richard D. Beckert, Phillip G. Hays, Steven P. Maillet, Andrew W. Lovitt
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Publication number: 20180295261Abstract: A fault tolerant display displays safety information on a display shared with an infotainment system even if the processor or software of the infotainment system is unresponsive. The display can be a streaming video from a rear view camera mounted on a vehicle. The safety displayed can be triggered by placing the vehicle in reverse. Failure of the infotainment software and/or processor can be detected by a policy enforcing module that switches to a backup display that streams video directly from the camera in the event of failure of the infotainment processor.Type: ApplicationFiled: June 14, 2018Publication date: October 11, 2018Inventors: Richard D. Beckert, Phillip G. Hays, Steven P. Maillet, Andrew W. Lovitt
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Publication number: 20140125802Abstract: A fault tolerant display displays safety information on a display shared with an infotainment system even if the processor or software of the infotainment system is unresponsive. The display can be a streaming video from a rear view camera mounted on a vehicle. The safety displayed can be triggered by placing the vehicle in reverse. Failure of the infotainment software and/or processor can be detected by a policy enforcing module that switches to a backup display that streams video directly from the camera in the event of failure of the infotainment processor.Type: ApplicationFiled: November 8, 2012Publication date: May 8, 2014Applicant: Microsoft CorporationInventors: Richard D. Beckert, Phillip G. Hays, Steven P. Maillet, Andrew W. Lovitt