Patents by Inventor Phillip G Williams
Phillip G Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11748104Abstract: Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.Type: GrantFiled: July 29, 2020Date of Patent: September 5, 2023Assignee: International Business Machines CorporationInventors: Bryan Lloyd, David A. Hrusecky, Sundeep Chadha, Dung Q. Nguyen, Christian Gerhard Zoellin, Brian W. Thompto, Sheldon Bernard Levenstein, Phillip G. Williams
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Publication number: 20220413911Abstract: A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Inventors: Brian W. Thompto, Michael Joseph Genden, Tharunachalam Pindicura, Phillip G. Williams, Kent Li, Nir Segev, Mehul Patel
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Patent number: 11392386Abstract: Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.Type: GrantFiled: August 14, 2020Date of Patent: July 19, 2022Assignee: International Business Machines CorporationInventors: Nicholas R. Orzol, Christian Gerhard Zoellin, Brian W. Thompto, Dung Q. Nguyen, Niels Fricke, Sheldon Bernard Levenstein, Phillip G. Williams, Brian D. Barrick
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Publication number: 20220050684Abstract: Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.Type: ApplicationFiled: August 14, 2020Publication date: February 17, 2022Inventors: Nicholas R. Orzol, Christian Gerhard Zoellin, Brian W. Thompto, Dung Q. Nguyen, Niels Fricke, Sheldon Bernard Levenstein, Phillip G. Williams, Brian D. Barrick
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Publication number: 20220035634Abstract: Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Inventors: Bryan Lloyd, David A. Hrusecky, Sundeep Chadha, Dung Q. Nguyen, Christian Gerhard Zoellin, Brian W. Thompto, Sheldon Bernard Levenstein, Phillip G. Williams
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Publication number: 20220019436Abstract: Provided is a method for fusing store instructions in a microprocessor. The method includes identifying two instructions in an execution pipeline of a microprocessor. The method further includes determining that the two instructions meet a fusion criteria. In response to determining that the two instructions meet the fusion criteria, the two instructions are recoded into a fused instruction. The fused instruction is executed.Type: ApplicationFiled: July 20, 2020Publication date: January 20, 2022Inventors: Bryan Lloyd, Sundeep Chadha, Dung Q. Nguyen, Christian Gerhard Zoellin, Brian W. Thompto, Sheldon Bernard Levenstein, Phillip G. Williams, Robert A. Cordes, Brian Chen
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Patent number: 11163571Abstract: Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.Type: GrantFiled: July 29, 2020Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Brian D. Barrick, Sundeep Chadha, Sheldon Bernard Levenstein, Phillip G. Williams, Niels Fricke, Dung Q. Nguyen, Brian W. Thompto, Christian Gerhard Zoellin
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Patent number: 10997075Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.Type: GrantFiled: May 13, 2019Date of Patent: May 4, 2021Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Hien M. Le, Hugh Shen, Derek E. Williams, Phillip G. Williams
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Patent number: 10983797Abstract: Processor instruction scheduling by: providing a set of program instructions, selecting instructions for reordering from the set of program instructions, reordering the instructions according to instruction properties, assigning sequential instruction tags to the instructions, tagging the instructions for completion as a group in a completion table; and executing the instructions.Type: GrantFiled: May 28, 2019Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Dung Q. Nguyen, Hung Q. Le, Jessica Hui-Chun Tseng, Jose E. Moreira, Sheldon Bernard Levenstein, Sundeep Chadha
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Publication number: 20200379766Abstract: Processor instruction scheduling by: providing a set of program instructions, selecting instructions for reordering from the set of program instructions, reordering the instructions according to instruction properties, assigning sequential instruction tags to the instructions, tagging the instructions for completion as a group in a completion table; and executing the instructions.Type: ApplicationFiled: May 28, 2019Publication date: December 3, 2020Inventors: Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Dung Q. Nguyen, Hung Q. Le, Jessica Hui-Chun Tseng, Jose E. Moreira, Sheldon Bernard Levenstein, Sundeep Chadha
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Patent number: 10467008Abstract: Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.Type: GrantFiled: May 31, 2016Date of Patent: November 5, 2019Assignee: International Business Machines CorporationInventors: David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr., Phillip G. Williams
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Patent number: 10437756Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.Type: GrantFiled: July 27, 2016Date of Patent: October 8, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Kurt A. Feiste, Brian W. Thompto, Phillip G. Williams
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Publication number: 20190294571Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Inventors: STEVEN R. CARLOUGH, KURT A. FEISTE, BRIAN W. THOMPTO, PHILLIP G. WILLIAMS
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Patent number: 10417152Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.Type: GrantFiled: June 3, 2016Date of Patent: September 17, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Kurt A. Feiste, Brian W. Thompto, Phillip G. Williams
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Publication number: 20190266093Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: Guy L. Guthrie, Hien M. Le, Hugh Shen, Derek E. Williams, Phillip G. Williams
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Patent number: 10387154Abstract: Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.Type: GrantFiled: March 14, 2016Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: James W. Bishop, Marcy E. Byers, Steven R. Carlough, Paul M. Kennedy, Albert J. Van Norstrand, Jr., Phillip G. Williams
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Patent number: 10331563Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.Type: GrantFiled: October 27, 2017Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Hien M. Le, Hugh Shen, Derek E. Williams, Phillip G. Williams
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Patent number: 10120683Abstract: Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor with null internal operations (IOPs) includes: receiving an IOP with an even ITAG requirement; determining that the IOP is to be assigned an odd ITAG; and inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.Type: GrantFiled: April 27, 2016Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Kurt A. Feiste, Paul M. Kennedy, Phillip G. Williams
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Publication number: 20180107510Abstract: Operation of a multi-slice processor implementing instruction fusion, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a first instruction that has an operand dependency on a second instruction in the set of instructions; and responsive to the first instruction having an operand dependency on the second instruction: issuing the first instruction and the second instruction to execute in parallel on the particular set of execution slices configured with fusion logic between execution slices that removes the operand dependency between the first instruction and the second instruction.Type: ApplicationFiled: October 19, 2016Publication date: April 19, 2018Inventors: STEVEN R. CARLOUGH, KURT A. FEISTE, DAVID R. TERRY, BRIAN W. THOMPTO, PHILLIP G. WILLIAMS
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Publication number: 20180052771Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.Type: ApplicationFiled: October 27, 2017Publication date: February 22, 2018Inventors: Guy L. Guthrie, Hien M. Le, Hugh Shen, Derek E. Williams, Phillip G. Williams