Abstract: An IC device bum-in system and method where a burn-in test motherboard is configured with a circuit environment like a customer level system motherboard. A stress software program is executed in a test controller which controls operational parameters to each IC device as well as determining whether an IC device runs system code or Built In Self Test (BIST) code. Running system or BIST code causes self heating which elevates the temperature levels for each IC device. Individual cooling means comprising cooling fans or thermoelectric coolers are used to control IC device temperatures to a desired burn-in level and to set temperature profiles. The stress software program may also adjust other operational parameters to the IC devices during a bum-in cycle. During a system level burn-in test the IC devices may undergo individual bum-in operation parameter profiles depending on the IC device part number.

Abstract: A computer-implemented method is provided in which a design layer of an integrated circuit is altered by spatial definition using underlying and overlying design layers. That is, the specific layers of an integrated circuit that impact the layer being modified are taken into account. According to an embodiment, the computer-implemented method is performed using, e.g., a CAD program. First, an original layout design comprising a plurality of design layers representing respective levels of an integrated circuit is generated. The targeted properties, e.g., electrical properties, of features in one design layer are determined based upon the arrangement of features in other design layers relative to the features in that one design layer. The features in the design layer being modified are then separated into different working layers such that each working layer includes features having at least one common targeted property.