Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.

Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.

Abstract: A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

Abstract: A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

Abstract: A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.

Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

Abstract: A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

Abstract: A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

Abstract: A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.

Abstract: Sensors on the integrated circuit are used to detect the current operating state of the chip, such as frequency, voltage, temperature characteristics, or variation in the integrated circuit manufacturing process. In response, the integrated circuit may choose to modify operational parameters (such as frequency, voltage, or power-down states) in order to dynamically and autonomously maintain an optimal performance and/or power-efficiency operational point.

Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.

Abstract: Sensors on the integrated circuit are used to detect the current operating state of the chip, such as frequency, voltage, temperature characteristics, or variation in the integrated circuit manufacturing process. In response, the integrated circuit may choose to modify operational parameters (such as frequency, voltage, or power-down states) in order to dynamically and autonomously maintain an optimal performance and/or power-efficiency operational point.

Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.

Abstract: A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.

Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.