Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

Abstract: Disclosed herein are methods of forming a replacement gate structure having a reentrant profile. In one example, the method includes forming a layer of material for a sacrificial gate electrode, wherein the layer of material includes at least one impurity that changes the etch rate of the layer of material as compared to an etch rate for the layer of material without the impurity, and wherein a concentration of the at least one impurity varies along a direction that corresponds to a thickness of the layer of material, and performing another etching process on the layer of material to define a sacrificial gate electrode. The method concludes with the steps of performing another etching process to remove the sacrificial gate electrode so as to at least partially define a gate opening in a layer of insulating material and forming a replacement gate structure in the gate opening.

Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

Abstract: A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

Abstract: Method and apparatus for etching an optically transparent layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for etching a substrate comprising placing the reticle on a support member in a processing chamber, positioning the reticle on a support member in a processing chamber, wherein the reticle comprises a patterned metal photomask layer formed on an optically transparent material, and a patterned resist material deposited on the patterned metal photomask layer, introducing a processing gas comprising one or more fluorine containing hydrocarbons and one or more chlorine-containing gases into the processing chamber, delivering power to the processing chamber to generate a plasma by applying a source RF power to a coil and applying a bias power to the support member, and etching exposed portions of the optically transparent material.

Abstract: A method in a plasma processing chamber for improving etch uniformity while etching a semiconductor substrate. The method includes placing the semiconductor substrate into a sacrificial substrate holder. The sacrificial substrate holder is configured to present a sacrificial etch portion surrounding the semiconductor substrate to a plasma within the plasma processing chamber to permit the plasma to etch a first surface of the semiconductor substrate and a first surface of the sacrificial etch portion simultaneously. The first surface of the sacrificial etch portion is formed of a material capable of being etched by the plasma. The method further includes positioning the semiconductor substrate and the sacrificial substrate holder into the plasma processing chamber. There is also included striking the plasma from an etchant source gas released into the plasma processing chamber.

Abstract: An apparatus and method in a plasma processing chamber for reducing charging of a wafer is described. A plasma generating element is configured to cause a plasma including ions and free radicals to be formed in a plasma generating region. A plasma diffusion region is configured so that plasma generated in the plasma generating region can diffuse through the plasma diffusion region. A conductive grid is positioned within the plasma diffusion region between the wafer and the plasma generating region. The conductive grid includes a mesh which is configured to trap a portion of the ions so that a portion of the ions are prevented from diffusing through the diffusion region to reach the wafer.

Abstract: The invention provides a gas discharge point of purchase display device. This device utilizes two flat vitreous glass plates, one of which contains a continuous channel of any desired shape, and together which form an ionization chamber. These vitreous plates are transparent; however provision is made for the incorporation of an opaque cover layer that conforms to the desired final illuminated geometry and which thus serves to obscure specified channel regions. The simple design of this sign makes possible the construction of these devices in quantity and at a relatively low cost by mass production methods.