Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: A method and apparatus for improvement of computer-related products by an independent developer may solve problems in hardware or software inadvertently, negligently, or intentionally left in products marketed by a vendor. An independent developer may procure access to a product, develop a testing regimen for functionality of the product, and perform evaluations to identify sources of any operational defects found. Accordingly, the developer may then provide a generalized testing regimen to test instances of product provided by a vendor, identify those containing the flaw, and may optionally provide a solution to the flaw, where practicable. The independent developer may obtain intellectual property rights in the testing, solution or both for the product. Thus, by notifying a vendor, an independent developer may become a supplier of testing or solution systems, motivating a supplier by one of several mechanisms.

Abstract: An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the cache is pinned, disabled from flushing the contents or replacing the contents of any cache line. A fast load may flush the cache and run an application containing the entire virtual machine instruction set. A pin manager may be hooked into a scheduler in a multi-tasking operating system to load, pin, and unpin the processor cache as rapidly as needed. Thus, the processor cache may be available for general use, except when pinned for use by a virtual machine, such as an interpretive environment. Level-1 caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention.

Abstract: A system and method which provides a complete software implementation of a detection process that is capable of detecting defective Floppy Diskette Controllers (“FDCs”) without visual hardware inspection or identification. The approach taken includes a multi-phase strategy incorporating programmatic FDC identification, software DMA shadowing, defect inducement, and use of a software decoding network which allows the implementation of the invention to adjust to a wide range of computer system performance levels. A method and apparatus for detecting and preventing floppy diskette controller data transfer errors in computer systems is also provided. The approach taken may involve software DMA shadowing and the use of a software decoding network.

Abstract: An apparatus and method for cache fencing allows programmatic control of the access and duration of stay of selected executables within processor cache. In one example, an instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, cache fencing is conducted to prevent the cache from flushing the contents or replacing the contents of any cache line. Typically, in so doing, attributes associated with pages in physical memory are employed. The attributes include an “uncacheable” attribute flag, which is set for the entire contents of physical memory except that containing the selected executables which are intended to remain within cache memory. The attributes may also include page sizing attributes which are utilized to define pages that contain interpreter instructions and pages that do not contain interpreter instructions.

Abstract: A system and method which provides a complete software implementation of a detection process that is capable of detecting defective Floppy Diskette Controllers (“FDCs”) without visual hardware inspection or identification. The approach taken includes a multi-phase strategy incorporating programmatic FDC identification, software DMA shadowing, defect inducement, and use of a software decoding network which allows the implementation of the invention to adjust to a wide range of computer system performance levels. A method and apparatus for detecting and preventing floppy diskette controller data transfer errors in computer systems is also provided. The approach taken may involve software DMA shadowing and the use of a software decoding network.

Abstract: An apparatus and method for cache fencing allows programmatic control of the access and duration of stay of selected executables within processor cache. In one example, an instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, cache fencing is conducted to prevent the cache from flushing the contents or replacing the contents of any cache line. Typically, in so doing, attributes associated with pages in physical memory are employed. The attributes include an “uncacheable” attribute flag, which is set for the entire contents of physical memory except that containing the selected executables which are intended to remain within cache memory. The attributes may also include page sizing attributes which are utilized to define pages that contain interpreter instructions and pages that do not contain interpreter instructions.

Abstract: A method and apparatus for providing media-independent security for a document may be programmed to create a document file having two or more components. In one embodiment, a document may include a background object, an image object (e.g. text, graphic, both, or the like), and a watermark object. When output, the image object is directly interpretable by a user. Meanwhile, in the background object, watermark object, or both, a high-resolution pattern may be stored to be output with all copies of the document. Encoded in some binary symbol in the pattern is security data. Resolution is high enough that the binary symbols are undetectable by a human eye. A processor may be programmed to recognize (e.g. read) the pattern, decode the pattern into binary data, and decode the binary data to characters directly interpretable by a user. Information relating to creation and control of a document, signature, or the like, may all be encoded independent from the principal image (e.g.

Abstract: A system and method for providing detection of the signatures effected by a defective Floppy Diskette Controller (“FDC”) operates on media independent of files thereon, or on files, independent of the media on which they are stored. Multiple testing strategies incorporate evaluations to detect signatures of data corruption introduced by defective FDCs from long transfer delays, short transfer delays, contiguous storage of logical sectors, or fragmented storage of logical sectors of a file. A false positive filter uses secondary testing of data. Filters remove from consideration those common patterns that properly and naturally occur. These filters rely on indicia demonstrating that primary leading indicators of the presence of an error do not really result from an actual error. The signatures may be detected regardless of subsequent transfer of corrupted files to various media including the media tested.

Abstract: An apparatus and method for accelerating interpretive environments may burst-load selected blocks of instructions into a processor cache. In an illustrated example, an interpretive instruction set implementing a virtual machine is modified to include a jump instruction embedded in each interpretive instruction. Each of the jump instructions points to a successive interpreter instruction, and the last jump instruction is a return to the main program. The interpretive instructions are crafted to occupy a single cache line as a compiled, linked, and loaded image. Consequently, burst-loading is accomplished by pointing to the jump instruction within an initial interpretive instruction. The cache registers a miss when the processor attempts to load the jump instruction, and a MMU loads a main memory block containing the initial interpretive instruction into a cache line. The jump instruction is executed, which results in the MMU loading a successive interpreter instruction into a cache line.

Abstract: A system and method which provides a complete software implementation of a detection process that is capable of detecting defective Floppy Diskette Controllers ("FDCs") without visual hardware inspection or identification. The approach taken includes a multi-phase strategy incorporating programmatic FDC identification, software DMA shadowing, defect inducement, and use of a software decoding network which allows the implementation of the invention to adjust to a wide range of computer system performance levels.

Abstract: An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the cache is pinned, disabled from flushing the contents or replacing the contents of any cache line. A fast load may flush the cache and run an application containing the entire virtual machine instruction set. A pin manager may be hooked into a scheduler in a multi-tasking operating system to load, pin, and unpin the processor cache as rapidly as needed. Thus, the processor cache may be available for general use, except when pinned for use by a virtual machine, such as an interpretive environment. Level-1 caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention.

Abstract: Flat-model, 32-bit, real-mode execution may be obtained in an INTEL.TM. X86-compatible processor of a computer to increase address space, while handling interrupts transparently. A protected-mode operating system is not required. A LOADALL instruction available to an operating system may load hidden cache descriptor registers of a processor with the base addresses, segment limits, and other attributes consistent with 32-bit, real-mode operation to provide 32-bit addressing. Interrupts, would normally interfere with the contents of the hidden cache descriptor registers. A new interrupt vector table is provided, with each new vector therein pointing to one of the new interposer routines provided. Upon receipt of an interrupt, a new interrupt vector points to an interposer routine, which saves the state of the hidden cache descriptor registers.

Abstract: A method and apparatus for providing media-independent security for a document may be programmed to create a document file having two or more components. In one embodiment, a document may include a background object, an image object (e.g. text, graphic, both, or the like), and a watermark object. When output, the image object is directly interpretable by a user. Meanwhile, in the background object, watermark object, or both, a high-resolution pattern may be stored to be output with all copies of the document. Encoded in some binary symbol in the pattern is security data. Resolution is high enough that the binary symbols are undetectable by a human eye. A processor may be programmed to recognize (e.g. read) the pattern, decode the pattern into binary data, and decode the binary data to characters directly interpretable by a user. Information relating to creation and control of a document, signature, or the like, may all be encoded independent from the principal image (e.g.

Abstract: A method and apparatus for directly accessing data compressed by a dictionary-based compression scheme are disclosed. The apparatus may include an execution unit for processing data and an address generation unit connected to the execution unit for generating a logical address corresponding to the data. A compressed memory address translation unit operably connected to the address generation unit maps the logical address to a linear address corresponding to a physical address at which the data is stored as compressed data. The compressed memory address translation unit may include comparison elements. Each comparison element is adapted to determine whether an input address is within an address range associated therewith. Each comparison element may further include a map logic circuit for computing the linear address as an offset and a base linear address. One single comparison element uniquely provides the linear address to be output by the compressed memory address translation unit.

Abstract: An apparatus and method for accelerating interpreters, interpretive environments, and the like optimizes the use of caches closest to a processor. An instruction set implementing a virtual machine (interpreter, interpretive environment) is written to fit each instruction at an individual cache line's address in the processor cache. The processor cache may be loaded with the instruction set in a compiled, linked, loaded image. After loading the processor cache, the cache is pinned, locked, disabled from flushing the contents or replacing the contents of any cache line. Faster loading of the processor cache may be achieved by flushing the processor cache and running an application containing all of the instructions of the virtual machine instruction set. Level-1 processor caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention. Examples include Intel's Pentium.TM. class products and Motorola's Power PC Processors.

Abstract: Description tables can be linked to a kernel to form a device driver. The description tables can be device description tables and adapter description tables. The kernel is operating system dependent. The description tables are operating system independent and can be linked to other kernels for other operating systems. A library of kernels for different operating systems can share a common set of kernel requests.

Abstract: Description tables can be linked to a kernel to form a device driver. The description tables can be device description tables and adapter description tables. The kernel is operating system dependent. The description tables are operating system independent and can be linked to other kernels for other operating systems. A library of kernels for different operating systems can share a common set of kernel requests.

Abstract: A system and method which provides a complete software implementation of a device driver that is capable of detecting an undetectable data corruption problem without hardware redesign and/or internal modification to an existing FDC. The approach taken consists of software DMA shadowing and use of a software decoding network which allows the implementation of the invention to require a small amount of memory and only degrade the performance of the computer system a minimal amount when floppy diskette write operations occur.