Abstract: A method and an apparatus for providing a float voltage potential in a bus connection are described. In one embodiment, a device has a first input, a second input, and an output. The first input is coupled to a first power supply and the second input is coupled to a second power supply. The device is configured to provide a float voltage potential at the output when the first and second power supplies supply the power at different time.

Abstract: A memory device including a nonvolatile memory cell, a bit line coupled to the nonvolatile memory cell, and circuitry coupled to the nonvolatile memory cell and the bit line. The circuitry is configured to reset the bit line to a predetermined state for an amount of time in response to a transition of an input address signal.

Abstract: A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.

Abstract: A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.

Abstract: Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.

Abstract: A programming verify circuit for controlling the memory cells to which programming voltages are applied, the circuit including a comparator for testing the state of each cell being programmed with the state to which the cell is being programmed, and a program load circuit which responds to the result of the test by the comparator to hold a condition for each memory cell being programmed to indicate whether the memory cell should be further programmed, each program load circuit including circuitry for precluding the holding of a condition indicating further programming is necessary once the associated memory cell has been initially verified as programmed by the comparator.