Abstract: In a microcoded central processing unit, apparatus and method are disclosed for permitting execution of a plurality of software programs, the secondary program being executed during no-op instructions for the primary program. The apparatus of the central processing unit is divided into two subunits capable of independent instruction execution for at least one timing cycle and referred to as master and slave portions. The memory unit storing the microcoded instruction word has two subunits, a subunit associated with the master portion and a subunit associated with the slave portion. Associated with each memory subunit is a microcode instruction word register that controls the operation of the associated portion of the central processing unit apparatus. Associated with each program is a microcode program counter that contains the address of the next instruction word in the program being executed.