Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

Abstract: Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.

Abstract: A high voltage AC power supply circuit for a capacitive load CL, such as an electroluminescent lamp, includes a low voltage DC supply, an inductor L and a FET S in series. The FET S can be pulsed so that the inductor L generates a voltage to charge the capacitive load CL via an H-bridge H, which is in parallel with the FET S. A diode D prevents current discharging from the capacitive load CL while the FET S is closed. The total capacitance downstream of the diode D and in parallel with the capacitive load CL is less than the capacitive load CL, so that when the polarity of the H-bridge is reversed, the voltage across the H-bridge collapses to earth and the capacitive load CL is discharged via the low voltage DC supply. The circuits which a employ a large smoothing capacitor in parallel with the H-bridge.