Abstract: Flying toy apparatus is provided including a housing with drive means provided therein for driving rotation of rotary means associated with said housing. Vane means are associated with said housing and said vane means rotate in a counter direction to the rotation of said rotary means in use. The vane means are arranged substantially vertically in use.

Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

Abstract: Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.

Abstract: Computer implemented method, system and computer program product for creating a resume that facilitates generating and updating multiple versions of the resume. A computer implemented method for creating a resume includes storing resume information. Rules are specified by which a resume for a particular job application is to be created, and the stored resume information is parsed according to the specified rules to provide specified resume information. A resume is then created for the particular job application from the specified resume information.

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.

Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of operation of the digital processing circuit, and a second timing circuit that provides timing signals to control timing of system operations during an active mode of operation of the radio frequency circuit. In one particular embodiment, at least a portion of the first timing circuit is disabled when the radio frequency circuit is active (receiving and/or transmitting).

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Abstract: A high voltage AC power supply circuit for a capacitive load CL, such as an electroluminescent lamp, includes a low voltage DC supply, an inductor L and a FET S in series. The FET S can be pulsed so that the inductor L generates a voltage to charge the capacitive load CL via an H-bridge H, which is in parallel with the FET S. A diode D prevents current discharging from the capacitive load CL while the FET S is closed. The total capacitance downstream of the diode D and in parallel with the capacitive load CL is less than the capacitive load CL, so that when the polarity of the H-bridge is reversed, the voltage across the H-bridge collapses to earth and the capacitive load CL is discharged via the low voltage DC supply. The circuits which a employ a large smoothing capacitor in parallel with the H-bridge.

Abstract: An audio system 100 includes circuitry 116 for generating an audio data stream and circuitry 103 for generating digital words defining a volume control level. System 100 also includes volume control circuitry 5000 for controlling the amplitude of the audio data stream in response to the digital words. Volume control circuitry 5000 includes a master register 5001 for holding digital words received from circuitry for generating 116 and a slave register 5002 for holding a digital word selectively transferred from master register 5001 in response to an enable signal. Output control circuitry 5005, 5006 and 5007 receive the audio data stream and apply a preselected gain defined by the digital word held in slave register 5002. Volume control circuitry 5000 also includes circuitry 5003, 5004 for generating the enable signal when a digital word held in the master register 5001 changes and the audio data stream output from ouput control circuitry 5005, 5006, 5007 reaches a zero crossing.

Abstract: Amplitude control circuitry 5000 includes a first register 5001 for storing received amplitude control data and a second register 5002 for storing amplitude control data transfered from first register 5001. Output circuitry 5005, 5006, 5007 controls the amplitude of a received signal in response to amplitude data transferred from second register. A sensor 5003 determines when data stored in first register 5001 and second register 5002 does not match and enables a comparator 5004 when data in first register 5001 and, second register 5002 does not match. Comparator 5004 compares a signal output from output circuitry 5005, 5006, 5007 with a reference signal and generates a signal for enabling the transfer of data from first register 5001 to second register 5002 when the signal output from output circuitry 5005, 5006, 5007 falls within a window defined by the reference voltage.

Abstract: A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Abstract: An audio system 100 includes digital-to-analog converters 110 having left and right paths for converting received left and right streams of digital audio data and a plurality of analog data ports for receiving left and right channel streams of analog audio data. Mixer 115 has left and right paths for selectively mixing left and right channel data passed from converters 110 and left and right channel data passed from the analog data ports. Muting circuitry is also provided for selectively muting said right and left channel data to be passed to mixer 115 from converters 110. Circuitry is also included for idling a selected one of the left and right paths of mixer 115 when selected data path to mixer 115 is muted.

Abstract: A model helicopter creates lift using rotor propellers mounted to the rotor arms of a gyroscopic rotor assembly. A controller converts front-back, and left-right inputs into speed control signals used to vary the speeds of the rotor propellers at selected positions of the rotor assembly as it rotates. The varying speed of the rotor propellers at selected rotor positions produces thrust vectors at those positions. The resultant thrust vector determines the direction of the helicopter's flight and enables it to pitch and roll in response to the front-back and left-right inputs. The rotor assembly can have two or more rotor arms, each with a propeller. The helicopter provides left-right yaw control with a yaw propeller on the helicopter body. Electric motors, or motors using other conventional power and speed control methods, can be used to drive the rotor and yaw propellers.