Patents by Inventor Phillip P. Normand
Phillip P. Normand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8826214Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.Type: GrantFiled: March 14, 2013Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Phillip P. Normand, II, Jason L. Van Vreede, Bradley C. White
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Patent number: 8689170Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.Type: GrantFiled: February 27, 2013Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Phillip P. Normand, Jason L. VanVreede, Bradley C. White
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Patent number: 8448121Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.Type: GrantFiled: August 11, 2011Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White
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Patent number: 8413104Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.Type: GrantFiled: May 12, 2011Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White
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Publication number: 20130042214Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White
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Patent number: 8356264Abstract: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.Type: GrantFiled: October 28, 2010Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Mark R. Lasher, Daniel R. Menard, Phillip P. Normand
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Publication number: 20120290995Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White
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Publication number: 20120110533Abstract: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark R. Lasher, Daniel R. Menard, Phillip P. Normand
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Patent number: 6990645Abstract: A method of analysis of an integrated circuit design having multiple voltage islands, including: (a) determining a clock path through the voltage islands; (b) determining a data path through the voltage islands; (c) determining which voltage islands are independent voltage islands; (d) determining which voltage islands are dependent voltage islands; (e) for the data path and the clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths; and (f) for the data path and the clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths.Type: GrantFiled: April 29, 2003Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Susan K. Lichtensteiger, Phillip P. Normand, Timothy M. Platt
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Publication number: 20040221252Abstract: A method of analysis of an integrated circuit design having multiple voltage islands, including: (a) determining a clock path through the voltage islands; (b) determining a data path through the voltage islands; (c) determining which voltage islands are independent voltage islands; (d) determining which voltage islands are dependent voltage islands; (e) for the data path and the clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths; and (f) for the data path and the clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths.Type: ApplicationFiled: April 29, 2003Publication date: November 4, 2004Applicant: International Business Machines CorporationInventors: Susan K. Lichtensteiger, Phillip P. Normand, Timothy M. Platt