Abstract: A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment has a length selected so as to be less than a quarter-wave resonance length of the conductive segment at the first frequency to thereby achieve duty cycle correction.

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

Abstract: The present invention is a system and method for optimizing electrical circuits by means of derivative-free optimization. Tunable parameters such as component values, transistor sizes or model parameters are automatically adjusted to obtain an optimal circuit. Any method of measuring the performance of the circuit, including computer simulation, can be incorporated into the optimization technique, with no derivative requirements. An arbitrary continuous optimization problem can be posed, including an objective function, equality and inequality constraints, and simple bounds on the tunable parameters. The optimization technique is efficient and guarantees that it will find a locally optimal solution from any starting point. Further, the procedure includes a method of automatically recovering from electrical failure to enable automatic and productive circuit optimization. A set of measurement widgets is provided to automatically introduce the checking required to recover from electrical failure.

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

Abstract: A supply noise compensation circuit. The supply noise compensation circuit senses the onset of dI/dt noise events on a supply line and selectively gates off/forces on a chip clock to chip circuits.

Abstract: The present invention is a system and method for optimizing electrical circuits by means of derivative-free optimization. Tunable parameters such as component values, transistor sizes or model parameters are automatically adjusted to obtain an optimal circuit. Any method of measuring the performance of the circuit, including computer simulation, can be incorporated into the optimization technique, with no derivative requirements. An arbitrary continuous optimization problem can be posed, including an objective function, equality and inequality constraints, and simple bounds on the tunable parameters. The optimization technique is efficient and guarantees that it will find a locally optimal solution from any starting point. Further, the procedure includes a method of automatically recovering from electrical failure to enable automatic and productive circuit optimization. A set of measurement widgets is provided to automatically introduce the checking required to recover from electrical failure.