Abstract: A switching apparatus for selectively transferring data packets between a plurality of local area networks (LANs) at full-wire speed. A shared memory is used to store in buffers data packets received from one LAN prior to their transfer to another LAN under control of a block of control logic. The control logic maintains and updates sets of pointers which identify and control access to the buffers in shared memory. A single processor monitors these pointers and in response to a single source address table further updates these pointers to direct the control logic to discard or alternatively to transfer received data packets to other LANs.