Abstract: The present disclosure generally pertains to optical communication apparatuses having field-tunable power characteristics. In one exemplary embodiment, an optical communication apparatus has an optical transmitter. The optical transmitter is coupled to logic that receives a user input indicative of a desired transmit mode for the transmitter, and the logic then dynamically tunes the transmitter's output power according to the selected transmit mode. In addition, the optical communication apparatus may have an optical receiver for receiving optical signals. The sensitivity of the receiver is controlled by a bias voltage that is applied to the receiver by the logic. The logic is configured to receive a user input indicative of a desired receive mode and then to tune the receiver's sensitivity via the bias voltage according to the selected receive mode.

Abstract: The present disclosure generally pertains to optical communication apparatuses having field-tunable power characteristics. In one exemplary embodiment, an optical communication apparatus has an optical transmitter. The optical transmitter is coupled to logic that receives a user input indicative of a desired transmit mode for the transmitter, and the logic then dynamically tunes the transmitter's output power according to the selected transmit mode. In addition, the optical communication apparatus may have an optical receiver for receiving optical signals. The sensitivity of the receiver is controlled by a bias voltage that is applied to the receiver by the logic. The logic is configured to receive a user input indicative of a desired receive mode and then to tune the receiver's sensitivity via the bias voltage according to the selected receive mode.

Abstract: A mechanism for implementing a single-interrupt-based voice playout buffer transfer operation. The contents of each respective channel of a multi-channel voice playout buffer are encapsulated so as to prepend a four byte ATM header, a HEC byte, and a four byte AAL2 header to a forty-four byte voice channel field to realize a standard fifty-three byte ATM cell. Within the AAL2 header, a channel identification byte (CID) provides selective mapping to timeslots of a TDM frame, to accommodate variations among different vendor equipments. The next to last bit of the last byte of the ATM header is used as an interrupt to the network processor. Only the highest voice channel asserts this next to last bit as an interrupt bit.

Abstract: A dual PHY-based integrated access device (IAD) platform employs a highly integrated time division multiplexed (TDM), a synchronous transfer mode (ATM) cell based architecture, to provide enhanced interfacing flexibility for multiple and diverse signaling protocols, effectively reducing the cost and constraints as to choice of host processor used in conventional digital signal processor (DSP)-based IADs. With the signaling transport speed of the dual PHY based path being an order of magnitude greater than that of any of the plurality of communication paths with which the IAD is interfaced, the IAD of the invention provides effectively real time support for different communication requirements, including TDM, ATM, HDLC, and the like.

Abstract: A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

Abstract: A voice path direct memory access (DMA)-based packet generation mechanism writes digitally encoded voice samples directly into prescribed subportions of a preallocated portion of random access memory, to avoid interrupting a main processor for the purpose. A pointer to a respective buffer space subportion is presented to a protocol stack, so that one or more overhead bytes for the stored voice samples can be generated and written into adjacent address space of the preallocated portion of random access memory. The contents of the preallocated memory space are then serialized out for transmission to a destination receiver.

Abstract: An operational condition capture mechanism within the communications control processor of an integrated access device stores in non-volatile (flash) memory prescribed state information associated with the operation of the communications control processor, in response to a catastrophic event that initiates a reboot of the device, and thereby interruption of the transmission of digital communication signals by the integrated access device, so as to facilitate subsequent off-line analysis (e.g., trouble-shooting) of the cause of the misoperation of the device, and interruption of digital communication service.

Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

Abstract: A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. A respective buffer section sequentially stores digitized voice signals of a single TDM channel into successive storage locations of a first portion thereof at a first data rate, and reads out digitized voice signals at a second, higher data rate for transport over an ATM cell bus. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

Abstract: A dual PHY-based integrated access device (IAD) platform employs a highly integrated time division multiplexed (TDM), a synchronous transfer mode (ATM) cell based architecture, to provide enhanced interfacing flexibility for multiple and diverse signaling protocols, effectively reducing the cost and constraints as to choice of host processor used in conventional digital signal processor (DSP)-based IADs. With the signaling transport speed of the dual PHY based path being an order of magnitude greater than that of any of the plurality of communication paths with which the IAD is interfaced, the IAD of the invention provides effectively real time support for different communication requirements, including TDM, ATM, HDLC, and the like.

Abstract: A mechanism for implementing a single-interrupt-based voice playout buffer transfer operation. The contents of each respective channel of a multi-channel voice playout buffer are encapsulated so as to prepend a four byte ATM header, a HEC byte, and a four byte AAL2 header to a forty-four byte voice channel field to realize a standard fifty-three byte ATM cell. Within the AAL2 header, a channel identification byte (CID) provides selective mapping to timeslots of a TDM frame, to accommodate variations among different vendor equipments. The next to last bit of the last byte of the ATM header is used as an interrupt to the network processor. Only the highest voice channel asserts this next to last bit as an interrupt bit.

Abstract: A voice path direct memory access (DMA)-based packet generation mechanism writes digitally encoded voice samples directly into prescribed subportions of a preallocated portion of random access memory, to avoid interrupting a main processor for the purpose. A pointer to a respective buffer space subportion is presented to a protocol stack, so that one or more overhead bytes for the stored voice samples can be generated and written into adjacent address space of the preallocated portion of random access memory. The contents of the preallocated memory space are then serialized out for transmission to a destination receiver.