Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Abstract: Methods and apparatus for controlling a flow of process material to a deposition chamber.

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Abstract: Methods and apparatus for controlling a flow of process material to a deposition chamber.

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Abstract: Embodiments of the present disclosure generally relate to organic vapor deposition systems and substrate processing methods related thereto. In one embodiment, a processing system comprises a lid assembly and a plurality of material delivery systems. The lid assembly includes lid plate having a first surface and a second surface disposed opposite of the first surface and a showerhead assembly coupled to the first surface. The showerhead assembly comprises a plurality of showerheads. Individual ones of the plurality of material delivery systems are fluidly coupled to one or more of the plurality of showerheads and are disposed on the second surface of the lid plate. Each of the material delivery systems comprise a delivery line, a delivery line valve disposed on the delivery line, a bypass line fluidly coupled to the delivery line at a point disposed between the delivery line valve and the showerhead, and a bypass valve disposed on the bypass line.

Abstract: Methods and apparatus for controlling a flow of process material to a deposition chamber.

Abstract: Embodiments described herein relate to methods for forming or treating material layers on semiconductor substrates. In one embodiment, a method for performing an atomic layer process includes delivering a species to a surface of a substrate at a first temperature, followed by spike annealing the surface of the substrate to a second temperature to cause a reaction between the species and the molecules on the surface of the substrate. The second temperature is higher than the first temperature. By repeating the delivering and spike annealing processes, a conformal layer is formed on the surface of the substrate or a conformal etching process is performed on the surface of the substrate.

Abstract: A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices.

Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.

Abstract: Methods and apparatus for semiconductor manufacturing process monitoring and control are provided herein. In some embodiments, apparatus for substrate processing may include a process chamber for processing a substrate in an inner volume of the process chamber; a radiation source disposed outside of the process chamber to provide radiation at a frequency of about 200 GHz to about 2 THz into the inner volume via a dielectric window in a wall of the vacuum process chamber; a detector to detect the signal after having passed through the inner volume; and a controller coupled to the detector and configured to determine the composition of species within the inner volume based upon the detected signal.

Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.

Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.